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Date:	Sun, 3 Jan 2016 14:38:49 -0500
Message-Id:	<201601031938.u03Jcnrt011354@envy.delorie.com>
From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
CC:	geda-user AT delorie DOT com
In-reply-to:	<56895EC2.80509@ecosensory.com> (message from John Griessen on
	Sun, 3 Jan 2016 11:47:46 -0600)
Subject:	Re: [geda-user] ideas on slotting and mechanisms for
	grouping/associating heterogenous symbols.
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> Maybe call it fpga-pin-swap for clarity.  The affected nets/pins
> could have wires drawn, and could go to slotted packages/symbols
> too.

The problem of assigning semantics to FPGA pins is slightly different,
because it's more complicated than just swapping pins (FPGA pins might
have interface limitations, clock domains, etc).  Still, the
developers can create a swap map for the fpga's layout where it makes
sense, although I suspect something like John's fpgas-as-tables to be
a better alternative.

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