Mail Archives: geda-user/2015/12/29/12:34:36
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On Dec 29, 2015, at 7:09 AM, Nicklas Karlsson =
(nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] =
<geda-user AT delorie DOT com> wrote:
>>> In my view it is only generic if all backends do exactly the same =
text
>>> processing and use exactly the same attribute names. I don't think
>>> that is generic enough. But I may be wrong.
>>=20
>> That leads you into same very difficult corners, since different =
downstream tools have different models of what a circuit is.
>>=20
>> John Doty Noqsi Aerospace, Ltd.
>> http://www.noqsi.com/
>> jpd AT noqsi DOT com
>=20
> Backends:
> Spice --> netlist, map symbol pins to electrical model?
> circuit board --> netlist, map symbol pins to footprint pins, BOM
> cables between circuit boards --> Schematic, BOM, cable thicknesses or =
types
A footprint is much like a SPICE model to a netlister: a set of ports =
that connect to nets. But there are fiddly details. SPICE is =
hierarchical, but most printed circuit layout systems aren=92t. =
Published SPICE models often reflect single slots, not complete =
packages. SPICE can put many more parameters on a component than you =
normally do for PCB layout. The electrical model for a physical =
component may either be an elementary device or a subcircuit. Should a a =
connector model be a subcircuit instance, a subcircuit declaration, or a =
collection of test points?
So, it isn=92t simply a matter of having =93exactly the same text =
processing=94. Until I wrote gnet-spice-noqsi, it wasn=92t possible to =
have a complicated schematic that was useful for both layout and =
simulation. It=92s still a fair amount of extra work in symbol =
preparation.
> ASIC --> ?
For my mixed-signal ASIC work I export SPICE. The layout contractor can =
take that as inputs. My SPICE netlists are hierarchical and may be =
simulated without modification: just add stimuli on top and process =
models on the bottom. The layout contractor can create =93parameter =
extracted=94 SPICE netlists at any hierarchical level from the physical =
layout with identical interfaces to my schematic-derived netlists for =
verification.
This works very smoothly with geda-gaf and ngspice. In some ways, to a =
schematic designer, it is the easiest and most rigorous gEDA flow I =
know.
> Verilog --> ?
> VDHL --> Connection of blocks is this structural VHDL?
For ASIC, these are similar to SPICE, I believe. In general, simulation =
to layout flows are hierarchical and ultimately based on the structural =
subset of the simulation language. But even in SPICE, you can decide to =
model a subcircuit behaviorally, and elementary models are always =
behavioral. So before layout, you may keep the option of simulating some =
blocks behaviorally for efficiency.
FPGA is similar: structural at high level, behavioral at low, but the =
boundary is more complicated.
After having written a makefile back end for gnetlist, I wonder about =
translating some sort of diagram into behavioral HDL code. The problems =
appear similar.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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