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	Sat, 24 Oct 2015 11:56:52 -0700 (PDT)
Date:	Sat, 24 Oct 2015 20:56:44 +0200
From:	"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] Star shorts
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> > On to PCB (or any other layout too; John Doty can close his ears for
> > this part).  AFAICT, there is no established technique to implement
> > such a star short in a way that will pass DRC.  There needs to be
> > copper half-inside the DRC process, that definitely shows up on the
> > Gerber output.  This copper can't exist during the netlist check
> > (optimize rats).
> 
> 
> > To my feeble brain (it's been a difficult week) it would make sense
> > to use a special-purpose layer for this job.  The star short component
> > would put copper on it.  it would show up as part of one layer
> > for every step except the rats processor.  I guess this extra layer
> > could be paired with any copper layer?  And you could have star
> > grounds (and this layer) for any copper layer?  The footprint would
> > have to be carefully designed (and maybe depend on the design rules?)
> > so that there's no chance of any copper, other than the wires attaching
> > to the star, touching the ghost copper that makes the short.
> >
> 
> Another option would be to somehow have pcb keep it's nose out of any
> connectivity that happens intra-footprint, since that's none of its
> business, and make overlapping pads.  I was going to propose this, and then
> realized that pcb would actually probably consider it a short.  So I think
>  the current behavior (assuming it does complain) is not intuitive.  This
> could lead to nasty results for broken footprints of course, but broken
> (e.g. pin-swapped) footprints are always nasty and there's nothing gEDA can
> do to catch that sort of thing.

I think pcb design rule check should care about copper regardless of how it have been created because that's what physics like ohms law care about.


Nicklas Karlsson

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