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Date:	Mon, 19 Oct 2015 23:04:23 +0200
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Subject:	Re: [geda-user] A lesson from gnet-makefile
From:	"Svenn Are Bjerkem (svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 19 October 2015 at 22:02, Evan Foss (evanfoss AT gmail DOT com) [via
geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
> Not everything Cadence has done is good.

Most things Cadence has done has been pure evil, that's how they
manage to stay one of the big three. For most small eda tool vendors
it has been plug into Composer, or die. Be conform to Composer, or
die. Try to replace Composer, and you will die. (after being bought by
Cadence or fought by Cadence i court).

All the semiconductor jobs I have had has been using Composer. There
are other tools, but somehow they all stick to Composer. It's like
Office and Microsoft.

Now I am doing FPGA so I have a more relaxed relationship to Cadence.
Problem is just the same: I want to capture the structure of my design
by schematic and fill the leaf nodes with VHDL behavioural code.
Problem is just that VHDL is not popular on the other side of the
Pond. There are some issues with buspins and netlisting, and I am not
understanding at all what is going on behind the code. Most of the
devs here seems only interested in making printed circuit boards, so I
try to back up those who target a generic front end editing tool with
mostly the same capabilities that Composer gave as a schematic capture
tool. Cadence may be evil, but Composer as a tool is a pure
productivity tool. It has to be if you want to create custom
schematics for ASICs with thousands (and more) of transistors.

If the guile API in gschem is covering enough exposed functionality,
the netlisting could probably be done in scheme from within gschem,
short-cutting gnetlist, but I don't know enough about the inner
workings of gschem to even dream of doing that. I am currently at the
level of cadar to re-learn lisp. Long way to go.

-- 
Svenn

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