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Date:	Wed, 9 Sep 2015 13:21:04 -0400
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From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
In-reply-to:	<alpine.DEB.2.00.1509091133300.2682@lichen> (message from Roland
	Lutz on Wed, 9 Sep 2015 11:45:50 +0200 (CEST))
Subject:	Re: [geda-user] New experimental netlist features
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> Do you have any suggestion for a less ambiguous syntax?

We resolve ambiguity by documenting what we expect.

The question is, which syntax makes the most sense for us - what would
present the "least surprise" to the user?

I think in this case, choosing between:

* Pascal
* Ada
* An obscure GCC extension[*]
* Verilog

Verilog is the obvious choice here, because it's a modern, relevent
(to us), and commonly used language.  For projects with both layout
and fpga it would be "natural" to use the same bus syntax for both
cases.

We can then document *extensions* to this syntax if we need to, for
example "lists of signals" might require a comma-separated list like
"netname=nWR,nRD,nCS,A[15:0],D[8:0]".


[*] I'm a gcc maintainer and even I keep forgetting it's there ;-)

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