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Date:	Wed, 26 Aug 2015 11:41:46 -0400
Message-ID:	<CAM2RGhQYJ94ZTcRx=xHgiBs8SMxLPVjm4XnrG7mM2joRf3XP0g@mail.gmail.com>
Subject:	Re: [geda-user] netlisting libraries (was: memory planning and pcb
	file format)
From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On Wed, Aug 26, 2015 at 10:37 AM, John Griessen <john AT ecosensory DOT com> wrote:
> On 08/25/2015 02:56 PM, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via
> geda-user AT delorie DOT com] wrote:
>>
>> It might work better you postpone the memory representation and figure
>> which kind of functions you need to access the objects. Then the access
>> functions are decided it will be easier to think about the representation.
>
> +1
>
> On 08/25/2015 04:05 PM, Evan Foss (evanfoss AT gmail DOT com) [via
> geda-user AT delorie DOT com] wrote:> On Tue, Aug 25, 2015 at 4:02 PM, DJ
> Delorie<dj AT delorie DOT com>  wrote:
>>> >
>>> >I wonder if gschem would be more plugin-friendly if there were more
>>> >operations that acted directly on the schematic you're editing.  PCB
>>> >has a lot of features/plugins that are "editors" of the pcb, but other
>>> >than gattrib most of the other gEDA tools work with a pre-existing
>>> >schematic.
>> Funny I always thought of that as the reason why PCB it lacks a
>> coherent concept of a layout.
>
> no, it's just the evolved spaghetti of internal code.
>
> The concept of "be an editor"  with the "schematic file as your database" is
> a simplifying one.
> Same for layout.  If gnetlist was an external library that could talk both
> ways it would be improved also.
>
> Think of the non-standard use case of creating a FPGA schematic that
> replaces a discrete logic chunk
> with a module that is only in verilog:
> Save the discrete logic to a new sch file, create a symbol for the verilog
> chunk,
> connect up after deleting the discrete logic, generate a new netlist.
> Generate a new netlist for the
> discrete part.
>
> Now you want to check things.  This is all new code for future.
> 1. generate a simulatable verilog-ams netlist from the verilog chunk.
> 2. create a simulation version schematic and generate simulatable
> verilog-ams netlist from the top interconnect.
> 3. concatenate and simulate together
> 4. create a simulation version schematic and generate simulatable
> verilog-ams netlist from the discrete logic.
> concatenate discrete logic verilog-ams netlist and verilog-ams netlist from
> the top interconnect.
> 5. They should be equal.

What excites you is not what excites me.

> I would not mind if all comparisons of back-annotated, simulation, carrying
> forward to layout
> were handled in a separate GUI, and set of commands put in a library so the
> several cases that always
> dominate peoples' thinking so they have a tough time planning code are
> separate and not such a problem.
>
> The translations from schem to netlist seem easy for programs to deal with
> as things scale up,
> but the internal design rule checks need speed help, and separating might
> allow thinking of speedy ways
> more easily.  I'm thinking towards printable electronics plus occasional
> FPGAs, which is down the road a bit,
> but possible for gEDA, probably never for IDE type FOSS ECAD tools we know.



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