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Mon, 27 Jul 2015 07:51:17 -0700 (PDT) | |
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Date: | Mon, 27 Jul 2015 20:21:17 +0530 |
Message-ID: | <CALT8Ef4rHxRL_4QhbKKNJhOXy2okUbPBNnOZia05hyxkQBqfZA@mail.gmail.com> |
Subject: | Re: [geda-user] high freq, trace lengths (was: pcb-rnd feature poll: |
please vote) | |
From: | "Shashank Chintalagiri (shashank DOT chintalagiri AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
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(a python object hierarchy) On Mon, Jul 27, 2015 at 8:18 PM, Shashank Chintalagiri <shashank DOT chintalagiri AT gmail DOT com> wrote: > Measuring trace lengths for a parallel bus is one of the things I'd > like to have as well. > > To that end (and various others), I've been working on a parser that > converts a PCB file into an object hierarchy. It's not even close to > doing anything useful yet, but I'm happy to share the core if you want > to use it. Of course, none of what I've written will actually work > _within_ pcb, but more as an external after-the-fact analysis tool. > > > > On Mon, Jul 27, 2015 at 7:34 PM, <gedau AT igor2 DOT repo DOT hu> wrote: >> >> >> On Mon, 27 Jul 2015, Ouabache Designworks (z3qmtr45 AT gmail DOT com) [via >> geda-user AT delorie DOT com] wrote: >> >>> What we need is a tool that can extract a spice model of the PCB from the >>> layout but I suspect that is beyond the scope for a open source project. >> >> >> Beyond my scope but not because open source but because I have no idea how >> to do it. We could team up: you do all the math and build test cases and I >> do the code. >> > > > > -- > > Chintalagiri Shashank > Indian Institute of Technology, Kanpur > > http://blog.chintal.in -- Chintalagiri Shashank Indian Institute of Technology, Kanpur http://blog.chintal.in
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