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Date: | Sat, 11 Jul 2015 23:22:37 +0000 |
Message-ID: | <CAM2RGhSGbQPriFoiLdEZVZXp804rVbXUorcUyVEnR9CNV0KPXw@mail.gmail.com> |
Subject: | Re: [geda-user] What is the hardest part in a PCB layout program? |
From: | "Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
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On Thu, Jul 9, 2015 at 9:57 PM, DJ Delorie <dj AT delorie DOT com> wrote: > >> The hardest part for me to understand when I look at the code is >> where the geometry is processed vs where it is rendered. > > This one is easy. Rendering is always done in the HID, like > src/hid/gtk or src/hid/ps. Everything in the core deals with the raw > data or its geometry directly. > >> OT: Is DRC checking done via the rendering engine or is there a >> separate geometry engine that does this and verifies when traces and >> etc are connected? > > There's a geometry engine in DRC although how it works is totally > counter-intuitive: > > * Generate a netlist based on connectivity. (also used by the rats > list stuff, find, select-nets, etc) > > * Now, increase the size of everything by N and generate a new netlist. > > * Are the netlists different? Bug! DJ Is there an architectural document that outlines the broad picture of how PCB works? (thinking i should try to write one if only for my own use) -- Home http://evanfoss.googlepages.com/ Work http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/
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