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Subject:	Re: [geda-user] Parts with internally connected pins
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On Fri, 12 Jun 2015, Kai-Martin Knaak wrote:

> Donald Tillman wrote:
>
>> My current approach, giving the shield pins the same pin number in the
>> footprint, isn't bad, the rats nest just complains about missing
>> connections.  And I can add the connections, it's not holding me up.
>
> In some cases, the redundant connection can be considered beneficial. E.g.
> the multiple ground pins of a micro controller. Or the shield of a CAT6
> RJ45 connector.
>
>
>> But I'm wondering if there's an approach that's more preferable, that's
>> more in line with the internals.
>
> How about this:
> 1) all internally connected pins receive the same pin number
> 2) the designer can attach an ignore flag in the layout tool to the rat.
>
> This would make pcb ignore the respective rat when it assembles the
> currently unmet rats nests.
>

This issue keeps popping up from time to time... My solution in my PCB 
fork is an "internal connections" list, which comes from pin attributes 
of the footprint. If a pin/pad is assigned to a group, pcb simply implies 
galvanic connection between the pin and any other pin in the same group.

Details: http://repo.hu/projects/pcb-rnd/intconn.html

Example: A 0 ohm SMD resistor has both pins in the same group so can be 
used as a bridge to remove a rat line. The resistor still needs to be 
added in gschem, but as a single-pin device connected anywhere to the 
network. This means if I move the resistor to bridge gaps at different 
section of the network (e.g. connect the pin of a different IC to the 
same network), I don't need to back-annotate the change to gschem.

Together with the nonetlist feature, I can place such jumpers in pcb 
without having to add them in ghschem at all.

Details: http://repo.hu/projects/pcb-rnd/nonetlist.html

I've been using these for more than a year now and they work well.
I kindly recommend implementing these features (and flagcomp, 
http://repo.hu/projects/pcb-rnd/flagcomp.html for supporting similar 
transitions) in mainline PCB.

Regards,

Igor2

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