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Subject:	Re: [geda-user] PCB autorouter doesn't create vias. Bug or user error ?
From:	Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au>
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I suggest that you run the autorouter before adding the plane, as the
auotrouter will not cut into a plane for you.
I haven't used the autorouter in years, but my normal flow with it was:
1. Fence off keep out areas with rectangles of copper.
2. Run the autorouter
3. Tidy up traces with the trace optimisers
4. Convert autorouted traces that should be planes/partial planes by
finding them, selecting found, removing the clearline flag, then overlaying
them with copper polygons.


On Mon, Mar 9, 2015 at 8:42 AM, Stelian Pop <stelian AT popies DOT net> wrote:

> On Sun, Mar 08, 2015 at 09:12:01PM +0100, Stelian Pop wrote:
>
> > I fail to see how this can be considered as a feature, especially
> > when it did work differently on the previous PCB version.
>
> Strangely, I just tried again with the 2011 version, and did
> encounter the same "feature".
>
> However, I am 100% sure that I did the autorouting a few years ago,
> with the 2011 version, and that it worked at that time (the file
> containing the design starts with:
>         # release: pcb 20110918
>         FileVersion[20070407]
>
> Stelian.
> --
> Stelian Pop <stelian AT popies DOT net>
>



-- 
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au

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<div dir=3D"ltr">I suggest that you run the autorouter before adding the pl=
ane, as the auotrouter will not cut into a plane for you.<div style>I haven=
&#39;t used the autorouter in years, but my normal flow with it was:</div><=
div style>1. Fence off keep out areas with rectangles of copper.</div><div =
style>2. Run the autorouter</div><div style>3. Tidy up traces with the trac=
e optimisers</div><div style>4. Convert autorouted traces that should be pl=
anes/partial planes by finding them, selecting found, removing the clearlin=
e flag, then overlaying them with copper polygons.</div><div style><br></di=
v></div><div class=3D"gmail_extra"><br><div class=3D"gmail_quote">On Mon, M=
ar 9, 2015 at 8:42 AM, Stelian Pop <span dir=3D"ltr">&lt;<a href=3D"mailto:=
stelian AT popies DOT net" target=3D"_blank">stelian AT popies DOT net</a>&gt;</span> wro=
te:<br><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-=
left:1px #ccc solid;padding-left:1ex"><span class=3D"">On Sun, Mar 08, 2015=
 at 09:12:01PM +0100, Stelian Pop wrote:<br>
<br>
&gt; I fail to see how this can be considered as a feature, especially<br>
&gt; when it did work differently on the previous PCB version.<br>
<br>
</span>Strangely, I just tried again with the 2011 version, and did<br>
encounter the same &quot;feature&quot;.<br>
<br>
However, I am 100% sure that I did the autorouting a few years ago,<br>
with the 2011 version, and that it worked at that time (the file<br>
containing the design starts with:<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 # release: pcb 20110918<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 FileVersion[20070407]<br>
<div class=3D"HOEnZb"><div class=3D"h5"><br>
Stelian.<br>
--<br>
Stelian Pop &lt;<a href=3D"mailto:stelian AT popies DOT net">stelian AT popies DOT net</a=
>&gt;<br>
</div></div></blockquote></div><br><br clear=3D"all"><div><br></div>-- <br>=
<div class=3D"gmail_signature">Stephen Ecob<br>Silicon On Inspiration<br>Sy=
dney Australia<br><a href=3D"http://www.sioi.com.au" target=3D"_blank">www.=
sioi.com.au</a><br></div>
</div>

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