Mail Archives: geda-user/2015/02/10/11:56:49
On 02/10/2015 03:00 AM, Chris Smith wrote:
> are you saying that the following analogies might hold:
>
> module1:1/port4 = op-amp-1.sym:1/pin4
> module1:1/module5:1/port2 = op-amp-1.sym:1/npn-1.sym:1/pin2
>
> (assuming op-amp-1.sym might actually be a sub-circuit.)
That's it. That's the needed information, (in whatever format), to be able to have schematics within schematics
down to discrete black boxes, such as active chips, R's, L's and C's in packages. It also lets you
connect to input wires of a logic function verilog block of code instead of a package. Then you create that
subcircuit by any means -- hopefully using the same model to verify it.
It can go down to a resistor or transistor model as well if the transmission line effects of how they are connected
are dealt with somehow. That much would be left up to the user, and would be like rules for connection pin
physical shape, orientation, smoothness.
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