X-Authentication-Warning:	delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient:	geda-user AT delorie DOT com
Date:	Tue, 20 Jan 2015 20:45:46 +0100
From:	Florian Teply <usenet AT teply DOT info>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] HIDDEN PINS IN A SYMBOL
Message-ID:	<20150120204546.00b769c3@aluminium.mobile.teply.info>
In-Reply-To:	<201501181858.t0IIwReR017605@envy.delorie.com>
References:	<CALSZ9gp08b7L5HMesdT3yX-di-0PsqqjRA0b0RKGbc4FtOm6rQ AT mail DOT gmail DOT com>
	<CAOFvGD5_is9FkcG_i5557_ejFHUqeyA3UhNNdP2-yXRrwk-PPg AT mail DOT gmail DOT com>
	<20150118110441 DOT 1a328bf1 AT aluminium DOT mobile DOT teply DOT info>
	<201501181858 DOT t0IIwReR017605 AT envy DOT delorie DOT com>
X-Mailer:	Claws Mail 3.9.0 (GTK+ 2.24.16; powerpc-unknown-linux-gnu)
Mime-Version:	1.0
X-MIME-Autoconverted:	from quoted-printable to 8bit by delorie.com id t0KJjvie012536
Reply-To:	geda-user AT delorie DOT com
Errors-To:	nobody AT delorie DOT com
X-Mailing-List:	geda-user AT delorie DOT com
X-Unsubscribes-To:	listserv AT delorie DOT com

Am Sun, 18 Jan 2015 13:58:27 -0500
schrieb DJ Delorie <dj AT delorie DOT com>:

> 
> > Slightly not directly related to symbols, but it always sstrikes me
> > as odd that some (actually most for that kind of part) manufacturers
> > decide to use four pins for the drain, but only one for the source
> > terminal.
> 
> I always assumed the drain was on the bottom of the wafer, and that
> the extra pins were for heat dissipation...  The OnSemi app note
> for their ChipFET line say:
> 
>  "The pin–out is similar to the TSOP–6 configuration, with two
>   additional drain pins to enhance power dissipation and thermal
>   performance."
> 
> The ST smd app note says this about their SO-8 package:
> 
>  "Since the drain pins serve the additional function of providing the
>   thermal connection to the package, . . ."
> 
> See also:
> http://electronics.stackexchange.com/questions/32511/why-so-many-pins-for-the-mosfets-drain

I knew I was missing something. Working in a small SiGe BiCMOS fab, I
didn't think about vertical MOSFETs or anything less than twin-well
processes for that matter. An in these kind of processes, all drains
are isolated from the substrate by at least one reverse-biased
junction...

Thanks for pointing in the right direction,
Florian

- Raw text -