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Date: | Wed, 23 Jul 2014 14:46:45 -0400 |
Message-ID: | <CAM2RGhSDhodNzBn5wh3=N5K-uujsOe4HXyY2HeWJ91L8bUtezA@mail.gmail.com> |
Subject: | Re: [geda-user] Re: Layers and footprints |
From: | Evan Foss <evanfoss AT gmail DOT com> |
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Having never done chip design I could be wrong in the following line of thought but I want to understand this. That still sounds more like a netlisting issue to me. I should think the subcircuit really just needs some special tag on it's page that will indicate the Rx, Cx and other reference designators will be altered after netlisting & tessellation on the layout. On Wed, Jul 23, 2014 at 10:34 AM, John Griessen <john AT ecosensory DOT com> wrote: > On 07/23/2014 01:18 AM, Evan Foss wrote: >> >> John thing that worries me is the alteration of gschem. Other than >> adding another label for marking a 3D model along with the footprint >> what alteration is really needed from gschem? > > > Some way for it to handle symbols just as it handles subschematics > the way verilog or verilog-ams does. Then you have hierarchy > with the ability to reuse modules even if they have the same name. > It's a huge change. Not likely to happen at all unless a need is perceived. > > The kinds of reasons for this would be using gschem in chip design. > Next would be for large scale planar circuits of printed electronics > where you are using verilog and verilog-ams to model the lowlevel function > of layout cells that can be repeated hundreds of times as part of a > circuit. For when we can layout printed resistors, caps, diodes, > transistors, > inductors -- not just wire -- and fabbed for cheap. > > Could take a while. -- Home http://evanfoss.googlepages.com/ Work http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/
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