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Message-ID: | <52F0E93A.7040803@iae.nl> |
Date: | Tue, 04 Feb 2014 14:20:58 +0100 |
From: | myken <myken AT iae DOT nl> |
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To: | geda-user AT delorie DOT com |
Subject: | [geda-user] Tutorial: VHDL with gEDA Version 2.0 |
Reply-To: | geda-user AT delorie DOT com |
Hello all, I've finally had some time to update my VHDL tutorial (thanks for all the supporting comments). After an educating discussion with Vladimir I decided to remove the Verilog to VHDL script I had included in the tutorial and made a little side-note concerning the issue (item 3 in the tutorial). It would be nice if someone would take a look at it and tell me if it could be helpful. http://www.myken.nl/tutorials/gEDA/gEDAVHDLtut01.html If it's up to standard and informative enough I would appreciate it if someone added it to the wiki, I have no access rights to do so. Again any comments are welcome. Thanks, Robert.
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