Mail Archives: geda-user/2013/10/27/15:06:51
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Thank you for your reply. I have found a 'cludge' solution - if I give all
my subcircuits the same refdes, then all the merging happens correctly.
Seems a pretty dirty way of doing it, though...
The hierarchy really just allows me to have one master schematic from which
I can move around all others in the design easily. The circuit is a stereo
audio application, so each circuit (of which there are six) will be used at
most twice, and I don't have many signals moving between subcircuits (five
at most).
I think my options are boiling down to:
1. Keep the hierarchy, with the cludgy subcircuit naming described above
2. Keep the hierarchy, but route power signals explicitly to each subcircuit
3. Get rid of the hierarchy, and pass multiple schematic names to gsch2pcb
Yours,
James.
On Sun, Oct 27, 2013 at 11:21 PM, Peter Clifton <pcjc2 AT cam DOT ac DOT uk> wrote:
> On Sun, 2013-10-27 at 21:16 +0430, James Jackson wrote:
> > Further to this, looking in the PCB Netlist dialog, I see that each of
> > my subcircuits also contains duplicate nets (i.e. for +15v, 0v etc).
> >
> >
> > How can I get gsch2pcb to merge given nets (as well as ICs, as above)
> > across subcircuits?
> >
>
> Looking at when I've done this in the past, I've manually exported power
> rails by connecting the appropriate power symbol to an IO export at the
> child level hierarchy level.
>
> IMO, connecting the hierarchy explicitly is superior (and less prone to
> errors) than trying to use flat net-names across the whole design.
>
> In that case, you might as well use a flat design, especially as it
> removes your ability to annotate nets with names in sub-circuits without
> connecting all such sub-circuits together!
>
>
> When I've been forced to strip out hierarchical names from a design for
> layout refdes, there was a kludge I implemented to map gschem logical
> refdes (X1/X3/R1) into a board specific refdes, such as R199.
>
> The kludge is a non-standard patch (to gnetlist), and requires a file of
> mappings between the hierarchical and board-level names. If you think it
> might be of use, I can point you in the right direction to try it.
>
>
> Could you explain the use-case you have for hierarchy, and roughly how
> many instances of a given circuit you're using?
>
> There might be easier ways to achieve what you want. In the past, for a
> handful of channels, I've used a "master" schematic which is then
> copied, and renumbered in a Makefile to produce the source-files for
> netlisting.
>
>
> Regards,
>
> --
> Peter Clifton <peter DOT clifton AT clifton-electronics DOT co DOT uk>
>
> Clifton Electronics
>
>
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<div dir=3D"ltr">Thank you for your reply. I have found a 'cludge' =
solution - if I give all my subcircuits the same refdes, then all the mergi=
ng happens correctly. Seems a pretty dirty way of doing it, though...<div>
<br></div><div>The=A0hierarchy=A0really just allows me to have one master s=
chematic from which I can move around all others in the design easily. The =
circuit is a stereo audio application, so each circuit (of which there are =
six) will be used at most twice, and I don't have many signals moving b=
etween subcircuits (five at most).</div>
<div><br></div><div>I think my options are boiling down to:</div><div><br><=
/div><div>1. Keep the=A0hierarchy, with the cludgy subcircuit naming descri=
bed above</div><div>2. Keep the=A0hierarchy, but route power signals explic=
itly to each subcircuit</div>
<div>3. Get rid of the=A0hierarchy, and pass multiple schematic names to gs=
ch2pcb</div><div><br></div><div>Yours,</div><div>James.</div></div><div cla=
ss=3D"gmail_extra"><br><br><div class=3D"gmail_quote">On Sun, Oct 27, 2013 =
at 11:21 PM, Peter Clifton <span dir=3D"ltr"><<a href=3D"mailto:pcjc2 AT ca=
m.ac.uk" target=3D"_blank">pcjc2 AT cam DOT ac DOT uk</a>></span> wrote:<br>
<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex"><div class=3D"im">On Sun, 2013-10-27 at 21:1=
6 +0430, James Jackson wrote:<br>
> Further to this, looking in the PCB Netlist dialog, I see that each of=
<br>
> my subcircuits also contains duplicate nets (i.e. for +15v, 0v etc).<b=
r>
><br>
><br>
> How can I get gsch2pcb to merge given nets (as well as ICs, as above)<=
br>
> across subcircuits?<br>
><br>
<br>
</div>Looking at when I've done this in the past, I've manually exp=
orted power<br>
rails by connecting the appropriate power symbol to an IO export at the<br>
child level hierarchy level.<br>
<br>
IMO, connecting the hierarchy explicitly is superior (and less prone to<br>
errors) than trying to use flat net-names across the whole design.<br>
<br>
In that case, you might as well use a flat design, especially as it<br>
removes your ability to annotate nets with names in sub-circuits without<br=
>
connecting all such sub-circuits together!<br>
<br>
<br>
When I've been forced to strip out hierarchical names from a design for=
<br>
layout refdes, there was a kludge I implemented to map gschem logical<br>
refdes (X1/X3/R1) into a board specific refdes, such as R199.<br>
<br>
The kludge is a non-standard patch (to gnetlist), and requires a file of<br=
>
mappings between the hierarchical and board-level names. If you think it<br=
>
might be of use, I can point you in the right direction to try it.<br>
<br>
<br>
Could you explain the use-case you have for hierarchy, and roughly how<br>
many instances of a given circuit you're using?<br>
<br>
There might be easier ways to achieve what you want. In the past, for a<br>
handful of channels, I've used a "master" schematic which is =
then<br>
copied, and renumbered in a Makefile to produce the source-files for<br>
netlisting.<br>
<div class=3D"HOEnZb"><div class=3D"h5"><br>
<br>
Regards,<br>
<br>
--<br>
Peter Clifton <<a href=3D"mailto:peter DOT clifton AT clifton-electronics DOT co DOT uk=
">peter DOT clifton AT clifton-electronics DOT co DOT uk</a>><br>
<br>
Clifton Electronics<br>
<br>
</div></div></blockquote></div><br></div>
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