Mail Archives: geda-user/2013/09/01/00:39:20
Joshua -
On Sat, Aug 31, 2013 at 03:27:30PM -0400, Joshua Lansford wrote:
> An argument for this type of language is that FPGAs are getting bigger and
> bigger but people aren't getting smarter and smarter.
Nicely said. I couldn't agree more.
> I wrote a proof of concept higher level language compiler which compiles
> down to synthesizable Verilog which can also be simulated by gEDA icarus.
> It is open source and hosted here:
> https://github.com/JEdward7777/VerilogExpress
Cool! I'll take a look ... in my copious free time :-p
I don't see any Makefile or README files though, I'm not much of a
java person, and I have never touched Eclipse. That may slow me down.
> Currently all the vars are stuck at 32 bits, but Verilog
> synthesizers generally get rid of unused bits anyway.
I don't understand that statement. I'm very interested in being
able to write generic numeric code, have it simulate (at first)
at "infinite" precision, then establish real-life bounds and precision
needs based on SNR goals, resulting in concrete scaled-fixed-point
variables. That is well beyond existing language capabilities.
> The same
> seems to be true with hardware development, but I am not aware of any other
> open source project working in this direction.
Another possibly related project is migen
https://github.com/milkymist/migen
- Larry
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