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From: | Abhijit Kshirsagar <abhijit86k AT gmail DOT com> |
Date: | Thu, 17 Jan 2013 11:51:49 +0530 |
Message-ID: | <CACNnPRmn1rLA8enjo6epUhyb2OTzoyzYzrj7S4qxHsHdfAeh-g@mail.gmail.com> |
Subject: | Re: [geda-user] gnetlist hierarchy uref order setting |
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>Interesting. Stuart seems not to have implemented refdes "munging" for all of the components he lists at http://www.brorson.com/gEDA/SPICE/x631.html. So does that count as a bug? > Put (hierarchy-traversal "disabled") in your gnetlistrc. Then I netlist subcircuits separately and > let SPICE do the hierarchy expansion. See > http://www.brorson.com/gEDA/SPICE/intro.html. I've looked through this - and it seems to be the same as the RF example that ships with the gEDA distribution. As i understand, I need to generate the cir files from the sub-schematics first, then netlist the top level schematics. Do most people use something like a makefile, when systems become large? Is there a makefile generator out there? I was hoping to have everything (including the SPICE simulation commands) in schematics only - so the end user only needs to keep gSCHEM open and navigate the hierarchy to see the entire design. ~Abhijit
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