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On Tue, 2012-12-11 at 11:01 -0600, John Griessen wrote: > On 12/10/12 16:48, Stefan Salewski wrote: > > Simulated annealing may be useful when we try to optimize the position > > of components. For toporouters we have the concept of cuts and cut > > capacity (distance of adjacent terminals in the constrained delaunay > > triangulation, space occupied by traces). If there is unused capacity, > > we may try to move components together to reduce PCB area and trace > > length. > > > > Are you studying the toporouter code Stefan? Not the 8k lines of C from Anthony -- the reasons should be obvious, see my earlier postings.
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