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Date:	Thu, 1 Nov 2012 14:34:49 -0400
Message-Id:	<201211011834.qA1IYnVd006430@envy.delorie.com>
From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
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Subject:	Re: [geda-user] The state of gEDA/gaf (Was gEDA/PCBs diversity, Was: Pin hole size)
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> Is there any plans to implement back annotation ? Sometimes slot
> swapping, pin swapping etc would be useful. Even adding components
> (I regularly forget some blocking capacitors) would be fine. But I
> understand that this has really low priority...

I wrote up some notes about this:

http://www.delorie.com/pcb/pin-mapping.html

It's part of this:

http://www.delorie.com/pcb/component-dbs.html

The idea is that symbols have a symbolic pin name, and the component
you choose maps those symbolic pin names to physical pin numbers and
slots.  Then, there is no "back" annotation; PCB tells gnetlist which
mappings/slottings it has, and gnetlist chooses from unused pins/slots
to satisfy new connections.

The only catch is, you need a way of uniquely identifying "that" gate
in a heirarchical schematic, independent of refdes.

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