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Date:	Wed, 24 Oct 2012 10:22:04 -0400
Message-ID:	<CAPYb0EFCARPnutMQBNBJEbiDaE7Wj3PttucDY4HYGC6nU42GSg@mail.gmail.com>
Subject:	Re: [geda-user] Trace width - best practices?
From:	Bob Paddock <bob DOT paddock AT gmail DOT com>
To:	geda-user AT delorie DOT com
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On Tue, Oct 23, 2012 at 3:24 PM, Jan Kasprzak <kas AT fi DOT muni DOT cz> wrote:

> Note that I don't want the whole net to be made from wider traces,
> only connections between some of the pins of the same net should be made wider.

These are better known as Fuses, and are generally a bad idea.
Not saying it is not very common, just consider the Fuse aspect.

> - this decoupling capacitor should be placed as close to this chip as possible
>
> or
>
> - these four connections together form a current loop, and the loop as a whole
>         should be made as short as possible

It would be great to mark segments of the same net with attributes in
both PCB and the schematic.

As to the Autorouter being able to do it I don't think any Autorouter
for any cost will be considering all issues that need thought about
for a while. Autorouters are great for things like memory and digital
buses, analog and power, not so much.  What I have below here was
written on a different list to a different question but the
information is relevant to yours:

============================================
It has to do with the self-resonance of the package.  Different
capacitance values may have the same package self-resonance, for
packages of the same size:

http://www.sigcon.com/Pubs/news/1_17.htm

Summed up in Intersil App. Note 1325:
   http://www.intersil.com/data/an/an1325.pdf

"Since the same package was used for each of the capacitors,
their high frequency responses are the same. Effectively, this
negates the use of the smaller capacitors!"

Articles by Howard Jonson on the subject:
http://www.sigcon.com/Pubs/pubsKeyword.htm#bypass%20capacitors


For anyone that is really into this kind of stuff I *STRONGLY*
recommended subscribing to the
Compliance Club, and reading all 102 (current issue) back issues:

Journal Issue #55 and #56 2004 explains the issue and the issues of
layout that I've never seen described anyplace else:

http://www.compliance-club.com/journal_article.aspx?artid=138 section
2.6 to 2.9.

[Note the pop-up at the bottom of the screen that forces you to check
a box to allow cookies, if you don't you can't subscribe.  It is free
to subscribe.]

Every layout I've ever seen puts the different values capacitors in
the same physical orientation next to each other.
This fails to account for magnetic flux interference between the packages.
[If someone is going to tell me there is not magnetic flux then you
have moved in the world of Scalar Potentials from the
Aharonov–Bohm Effect & E. T. Whittaker .]

Self-resonance (package), ESR, ESL, capacitance value, magnetic flux
(layout), frequencies of interest, number of board layers, all have to
be accounted for, which means it is not as easy as paralleled values
[or changing trace widths in the middle of a net] is good or
paralleled values is bad.
 Makes this job such fun...

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