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Date: | Wed, 24 Oct 2012 02:42:22 +0200 |
From: | Kai-Martin Knaak <kmk AT familieknaak DOT de> |
To: | geda-user AT delorie DOT com |
Subject: | Re: [geda-user] Trace width - best practices? |
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--Sig_/o/9nMwk3+uvzb=52Jp7CIv4 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au> schrieb am 24. October 2012: > > Note that I don't want the whole net to be made from wider traces, > > only connections between some of the pins of the same net should be > > made wider. This is the tricky part. You want to divide a net in high current and low current parts. This calls for modifications in the data structure. The current data structure assumes that every segment of a net is equivalent. =20 > That would be nice. We could change the auto-placer to act on hints > like that. The current auto-placer is unfortunately very weak I have yet to see an autoplacer that is not "very weak" ;-) If full fledged autoplacement is too hard, then how about some human assisted solution? Say, you manually group components on the schematic. And pcb places these components in nicely divided groups, rather than in one large lump. ---<)kaimartin(>--- --=20 Kai-Martin Knaak kmk AT lilalaser DOT de http://lilalaser.de/blog --Sig_/o/9nMwk3+uvzb=52Jp7CIv4 Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEARECAAYFAlCHOW4ACgkQt9RkiGwLn1NNawCdFgUjdylJPZPl2Clre/v6MOch hIkAnRI1PuE8jUJWc9N/do8wBk9uKMWQ =k2UP -----END PGP SIGNATURE----- --Sig_/o/9nMwk3+uvzb=52Jp7CIv4--
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