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Date:	Mon, 12 Mar 2012 15:15:14 -0400
Message-Id:	<201203121915.q2CJFEHH015163@envy.delorie.com>
From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
In-reply-to:	<4F5E4A9F.6080102@neurotica.com> (message from Dave McGuire on
	Mon, 12 Mar 2012 15:12:31 -0400)
Subject:	Re: [geda-user] Very confused...possible PCB bug? Need help.
References:	<4F5DCE76 DOT 1060304 AT neurotica DOT com> <201203121526 DOT q2CFQgFn006867 AT envy DOT delorie DOT com> <4F5E4A9F DOT 6080102 AT neurotica DOT com>
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>    Someone mentioned "the zero-length trace problem" in private
> email; what's up with that?  I haven't googled it yet but I will in
> a moment.

If you have a trace that's so small as to be completely hidden under a
pin or pad, with the "join" flag set, then if that trace will
"connect" to a polygon even if the clearance around the pin/pad means
it really doesn't.

I.e. DRC doesn't consider pin clearance when checking to see if a
trace connects to a polygon.

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