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Date:	Tue, 21 Feb 2012 01:27:31 +0100
From:	Kai-Martin <kmk AT familieknaak DOT de>
Subject:	Re: [geda-user] verilog question - blocking/non-blocking
To:	geda-user AT delorie DOT com
In-Reply-To:	<4F41CB0A.2020902@optonline.net> (from geneglick@optonline.net
	on Mon Feb 20 05:24:42 2012)
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On 02/20/2012 05:24:42 AM, gene glick wrote:

> always @(posedge clk)
>  begin
>     count <=3D count + 1;   // non-blocking method
>     if (count =3D=3D 0)
>       do_something
>  end
> -------------------------------------------
(...)
> The second way, do_something occurs when the count is 1. Subtle
> difference. I don't have a synthesis tool ready to run, otherwise
> I'd try it. Question : does one method synthesize significantly
> different logic than the other?

Don't know about verilog. But VHDL compilers complain and refuse to
synthesize such constructs inside a block. A block is the VHDL way to
say that things should be done in parallel. Inside a process the snippet
would be fine, since commands are executed sequentially.

---<)kaimartin(>---
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Kai-Martin Knaak
Email: kmk AT familieknaak DOT de
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