Mail Archives: geda-user/2012/02/20/12:52:30
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Typical synthesizers will synthesize your two examples identically,
and that will cause you trouble.
On 02/19/2012 08:24 PM, gene glick wrote:
> consider this code:
>
> always @(posedge clk) begin count = count + 1; // blocking
> method if (count == 0) do_something end
Ack! Bad! in two ways: Screaming opportunities for races within
your verilog, and almost certainly your hardware and simulation
will differ.
As a rule, assignments to clocked signals ("count" in this case)
should use non-blocking assignment as below. The other rule is
that "always" blocks that model combinational logic should use
blocking assignments instead.
>
> then this way . . .
>
>
> always @(posedge clk) begin count <= count + 1; // non-blocking
> method if (count == 0) do_something end
Better. This will act more like your hardware. The scheduling
of processing in response to your clk will work differently.
Remember, Verilog is a modeling language, and an imperfect one at
that. It does pretty well, but it does not exactly capture all the
subtleties of real hardware. That normally doesn't matter, but you
can mess with your own head if you are not careful. The rules of
thumb above help make the scheduler work in your favor to give a
good simulation of the real hardware.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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