Mail Archives: geda-user/2011/11/18/05:39:02
>without anything suggesting the type of chip the file is actually targeted at,
>and nothing declaring how the internal signals are mapped to the
device's pins.
>
Your verilog code won't say any of that. The first level design entry is
more or less, functional (this is what makes the code portable from chip
vendor A to chip vendor B). Even though you are drawing a schematic in
this case, and trying to output verilog - the verilog code will replace
the explicit wires you drew with logical 'implied' connections, which
all the backend tools understand. Sort of like:
A = some output
B = some input
C = some input
A = B or D;
The backend stuff understands that the input pin B and C are connected
to some OR gate.
Chip and pin assignment happen with the manufactures tools, either
through gui or configuration files - your choice.
In the past, I have used Aldec Active-HDL, which is a really great tool,
for design entry (vhdl, verilog and/or schematic). It then interfaces
with Altera or Xilinx or Lattice in a way that you don't have to know
the backend tools at all. Nice.
Lately, I have been using Icarus Verilog and GTKWave to simulate
designs. When satisfied with the results, move onto the Altera or
Xilinx stuff. So now I have to learn the backend tools - but for the
simple stuff, it's simple enough.
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