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Sender:	silicon DOT on DOT inspiration AT gmail DOT com
Date:	Thu, 27 Oct 2011 07:57:45 +1100
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Subject:	[geda-user] Route Styles loading bug
From:	Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au>
To:	geda-user AT delorie DOT com
Reply-To:	geda-user AT delorie DOT com

Recent changes to PCB have created a bug that occurs when saving then
loading a PCB.  Applies to git head.

Steps to reproduce:

1. Open PCB
2. Observe all four Route Styles have the correct default values
3. Save the layout
4. Open layout in text editor and observe Styles declaration looks like this:
Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"]
5. Close PCB application
6. Launch PCB application
7. Load layout saved in step 3
9 Observe all four Route Styles have loaded incorrectly:
eg 10.00 mil -> 0.10 mil
   36.00 mil -> 4.00 mil

I'll hold off submitting a launchpad bug report for a few days, as I
guess it's likely this one will have a quick fix.

--
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$49 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47

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