Mail Archives: geda-help/2021/04/25/20:31:47
--Apple-Mail=_50B83283-6333-4458-8760-F98199B9BA85
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
charset=utf-8
Chad,
Sorry for the late response. I had a death in the family and have =
fallen behind in correspondence.
> On Apr 19, 2021, at 8:23 AM, Chad Parker (parker DOT charles AT gmail DOT com) =
[via geda-help AT delorie DOT com] <geda-help AT delorie DOT com> wrote:
>=20
> Hi Roger-
>=20
> Sorry for the frustration.=20
It happens=E2=80=A6its all in how we deal with it. Life, software, most =
other things...;^)
> I believe that DRC warning is somewhat recently added. One of the =
flags that can be set on many objects is called the "clearline" flag. =
This flag is used to indicate that a particular object (line, arc, via) =
should create a clearance around itself inside of polygons. If this flag =
is NOT set, then that clearance is not created, and the object is =
electrically connected to the polygon.
>=20
> The assumption is that if the clearline flag is NOT set, that the user =
wants that particular object to be connected to a polygon. So, DRC =
checks to see if that's the case, and if an object does not have the =
clearline flag set and is not touching a polygon, it raises a warning. =
So, in your case, I would suggest looking at the objects in question and =
checking these flags. If you have any objects that are not connected to =
polygons that also do not have the clearline flag set, you can set the =
clearline flag and that should make the warning go away.
>=20
> If you've reviewed the area and are confident that the design meets =
your requirements, then you can probably ignore those errors. Their =
primary purpose is to make sure that pcb did what you intended.
>=20
> I've worked pretty hard to make sure the DRC works as advertised, but =
it's always possible that there's a bug. The whole system is based on a =
suboptimal framework that I've been upgrading slowly. If you believe =
you've found a bug, it would be very helpful if you could file a bug =
report or send me a pcb file that demonstrates the behavior that you =
believe is an error.
Thank you for the insight into what may have been going on. I believe =
you are the right path to the problem I was having. My solution
was brute force however not seeing anything amiss with either the =
polygons or lines that were intended to be connected to them. I=20
still have no idea on what caused the error to appear. I am suspicious =
of the vias though.
My solution was to remove polygons and see what DRC did afterwards. When =
I was finally down to one polygon and a few errors, I began
to remove lines and vias to see what the effect would be. Lines that =
were to be connected to poly were. Vias seemed to be connecting
from top to bottom polygons where I would expect. However when I removed =
the last via from top to bottom copper the last DRC error
disappeared. I put back the via and the line to it and no errors cropped =
up. I then redid all the poly areas, vias and lines checking at each
edit for DRC errors. None occurred. It seemed like I must have done =
something to change a clear line flag somewhere, maybe on a
via, by accident. =20
I=E2=80=99ve never seen this error before so I am assuming cockpit error =
or clumsy fingers. Right now I have a clean DRC and am preparing
to send for fabrication. Thank you for your work on the DRC and on =
making PCB a usable tool. I truly appreciate your efforts.
Take care and thanks again for your response,
Roger Traylor
>=20
> Thanks,
> --Chad
>=20
> On Sun, Apr 18, 2021 at 3:38 AM Roger Traylor (traylor AT engr DOT orst DOT edu =
<mailto:traylor AT engr DOT orst DOT edu>) [via geda-help AT delorie DOT com =
<mailto:geda-help AT delorie DOT com>] <geda-help AT delorie DOT com =
<mailto:geda-help AT delorie DOT com>> wrote:
> Folks,
>=20
> Was putting final touches on a design and after some edits now I get
> multiple "joined line/via not connected to polygon" errors. I had been=20=
> increasing the line width of a few traces and little else.=20
>=20
> I quit the tool hoping for some resolution as I had seen some errors =
related
> to incorrect serial numbers on undo=E2=80=99s. I saved and restarted =
as the tool advised=20
> so undoing to get back to square one is not an option.
>=20
> I have looked at most of the errors flagged. They are all in an area =
where=20
> both top and bottom layers (2.4Ghz, 2 layers) can be used as ground =
planes.
> Many of the traces have never had a connection to either plane and =
furthermore=20
> I did not touch them in the final edit session. Others have always =
been=20
> connected to the ground plane via a join(on top) followed by a via to =
both sides
> using thermal tool to connect to both planes.
>=20
> I think DRC is lying to me. Have looked for hours but cannot find what =
is
> going on. The only difference in the pieces of the polygons I can find =
is that
> the object report for most is =E2=80=9Cclearly, selected,fullpoly=E2=80=9D=
while one other piece
> includes =E2=80=9Cfound=E2=80=9D. Can someone throw me a idea?=20
>=20
> Running PCB 4.2.2 on Ubuntu 19.10.
>=20
> Thanks in advance,
> Roger Traylor
--Apple-Mail=_50B83283-6333-4458-8760-F98199B9BA85
Content-Transfer-Encoding: quoted-printable
Content-Type: text/html;
charset=utf-8
<html><head><meta http-equiv=3D"Content-Type" content=3D"text/html; =
charset=3Dutf-8"></head><body style=3D"word-wrap: break-word; =
-webkit-nbsp-mode: space; line-break: after-white-space;" =
class=3D"">Chad,<div class=3D"">Sorry for the late response. I had =
a death in the family and have fallen behind in correspondence.<br =
class=3D""><div><br class=3D""><blockquote type=3D"cite" class=3D""><div =
class=3D"">On Apr 19, 2021, at 8:23 AM, Chad Parker (<a =
href=3D"mailto:parker DOT charles AT gmail DOT com" =
class=3D"">parker DOT charles AT gmail DOT com</a>) [via <a =
href=3D"mailto:geda-help AT delorie DOT com" =
class=3D"">geda-help AT delorie DOT com</a>] <<a =
href=3D"mailto:geda-help AT delorie DOT com" =
class=3D"">geda-help AT delorie DOT com</a>> wrote:</div><br =
class=3D"Apple-interchange-newline"><div class=3D""><div dir=3D"ltr" =
class=3D""><div class=3D"">Hi Roger-</div><div class=3D""><br =
class=3D""></div><div class=3D"">Sorry for the =
frustration. </div></div></div></blockquote><div><br =
class=3D""></div><div>It happens=E2=80=A6its all in how we deal with it. =
Life, software, most other things...;^)</div><br class=3D""><blockquote =
type=3D"cite" class=3D""><div class=3D""><div dir=3D"ltr" class=3D""><div =
class=3D"">I believe that DRC warning is somewhat recently added. One of =
the flags that can be set on many objects is called the "clearline" =
flag. This flag is used to indicate that a particular object (line, arc, =
via) should create a clearance around itself inside of polygons. If this =
flag is NOT set, then that clearance is not created, and the object is =
electrically connected to the polygon.</div><div class=3D""><br =
class=3D""></div><div class=3D"">The assumption is that if the clearline =
flag is NOT set, that the user wants that particular object to be =
connected to a polygon. So, DRC checks to see if that's the case, and if =
an object does not have the clearline flag set and is not touching a =
polygon, it raises a warning. So, in your case, I would suggest looking =
at the objects in question and checking these flags. If you have any =
objects that are not connected to polygons that also do not have the =
clearline flag set, you can set the clearline flag and that should make =
the warning go away.</div><div class=3D""><br class=3D""></div><div =
class=3D"">If you've reviewed the area and are confident that the design =
meets your requirements, then you can probably ignore those errors. =
Their primary purpose is to make sure that pcb did what you intended.<br =
class=3D""></div><div class=3D""><br class=3D""></div><div class=3D"">I've=
worked pretty hard to make sure the DRC works as advertised, but it's =
always possible that there's a bug. The whole system is based on a =
suboptimal framework that I've been upgrading slowly. If you believe =
you've found a bug, it would be very helpful if you could file a bug =
report or send me a pcb file that demonstrates the behavior that you =
believe is an error.<br class=3D""></div></div></div></blockquote><div><br=
class=3D""></div><div>Thank you for the insight into what may have been =
going on. I believe you are the right path to the problem I was having. =
My solution</div><div>was brute force however not seeing anything =
amiss with either the polygons or lines that were intended to be =
connected to them. I </div><div>still have no idea on what =
caused the error to appear. I am suspicious of the vias =
though.</div><div><br class=3D""></div><div>My solution was to remove =
polygons and see what DRC did afterwards. When I was finally down to one =
polygon and a few errors, I began</div><div>to remove lines and vias to =
see what the effect would be. Lines that were to be connected to poly =
were. Vias seemed to be connecting</div><div>from top to bottom =
polygons where I would expect. However when I removed the last via from =
top to bottom copper the last DRC error</div><div>disappeared. I put =
back the via and the line to it and no errors cropped up. I then =
redid all the poly areas, vias and lines checking at each</div><div>edit =
for DRC errors. None occurred. It seemed like I must have done something =
to change a clear line flag somewhere, maybe on a</div><div>via, by =
accident. </div><div><br class=3D""></div><div>I=E2=80=99ve never =
seen this error before so I am assuming cockpit error or clumsy fingers. =
Right now I have a clean DRC and am preparing</div><div>to send for =
fabrication. Thank you for your work on the DRC and on making PCB a =
usable tool. I truly appreciate your efforts.</div><div><br =
class=3D""></div><div>Take care and thanks again for your =
response,</div><div><br class=3D""></div><div>Roger =
Traylor</div><div><br class=3D""></div><br class=3D""><blockquote =
type=3D"cite" class=3D""><div class=3D""><div dir=3D"ltr" class=3D""><div =
class=3D""><br class=3D""></div><div class=3D"">Thanks,</div><div =
class=3D"">--Chad<br class=3D""></div></div><br class=3D""><div =
class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Sun, Apr =
18, 2021 at 3:38 AM Roger Traylor (<a =
href=3D"mailto:traylor AT engr DOT orst DOT edu" =
class=3D"">traylor AT engr DOT orst DOT edu</a>) [via <a =
href=3D"mailto:geda-help AT delorie DOT com" =
class=3D"">geda-help AT delorie DOT com</a>] <<a =
href=3D"mailto:geda-help AT delorie DOT com" =
class=3D"">geda-help AT delorie DOT com</a>> wrote:<br =
class=3D""></div><blockquote class=3D"gmail_quote" style=3D"margin:0px =
0px 0px 0.8ex;border-left:1px solid =
rgb(204,204,204);padding-left:1ex">Folks,<br class=3D"">
<br class=3D"">
Was putting final touches on a design and after some edits now I get<br =
class=3D"">
multiple "joined line/via not connected to polygon" errors. I had been =
<br class=3D"">
increasing the line width of a few traces and little else. <br class=3D"">=
<br class=3D"">
I quit the tool hoping for some resolution as I had seen some errors =
related<br class=3D"">
to incorrect serial numbers on undo=E2=80=99s. I saved and restarted as =
the tool advised <br class=3D"">
so undoing to get back to square one is not an option.<br class=3D"">
<br class=3D"">
I have looked at most of the errors flagged. They are all in an area =
where <br class=3D"">
both top and bottom layers (2.4Ghz, 2 layers) can be used as ground =
planes.<br class=3D"">
Many of the traces have never had a connection to either plane and =
furthermore <br class=3D"">
I did not touch them in the final edit session. Others have always been =
<br class=3D"">
connected to the ground plane via a join(on top) followed by a via to =
both sides<br class=3D"">
using thermal tool to connect to both planes.<br class=3D"">
<br class=3D"">
I think DRC is lying to me. Have looked for hours but cannot find what =
is<br class=3D"">
going on. The only difference in the pieces of the polygons I can find =
is that<br class=3D"">
the object report for most is =E2=80=9Cclearly, selected,fullpoly=E2=80=9D=
while one other piece<br class=3D"">
includes =E2=80=9Cfound=E2=80=9D. Can someone throw me a idea? <br =
class=3D"">
<br class=3D"">
Running PCB 4.2.2 on Ubuntu 19.10.<br class=3D"">
<br class=3D"">
Thanks in advance,<br class=3D"">
Roger Traylor<br class=3D"">
</blockquote></div>
</div></blockquote></div><br class=3D""></div></body></html>=
--Apple-Mail=_50B83283-6333-4458-8760-F98199B9BA85--
- Raw text -