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Mail Archives: geda-help/2016/07/29/18:03:50

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Subject: Re: [geda-help] pcb: blind via
To: geda-help AT delorie DOT com
References: <20160728160657 DOT 7f68f787 AT debian>
<20160728174027 DOT 453b2b41 AT debian DOT olsr> <20160728192015 DOT 4fc84ce8 AT debian DOT olsr>
<201607282248 DOT u6SMmTxw006065 AT envy DOT delorie DOT com>
From: "Milan Prochac (milan AT prochac DOT sk) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com>
Message-ID: <f3e69165-857d-c541-33d1-557fc93172a4@prochac.sk>
Date: Sat, 30 Jul 2016 00:03:27 +0200
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> * How is a blind/buried via represented internally?  Can that
>    represent all possibilities that a FAB house can make?
>
> * How do you edit them in the GUI, or even draw them on the screen?
>
> * What changes to the file format will be needed?  Are they backward
>    compatible?
>
> * What about DRC, optimizers, autorouters, and exporters?  Do they
>    need changes to handle them?
>
> * What about the gerber exports?  How do we break down the drills so
>    that FABs "just know" what to do with them?
>
> What makes this a tough problem is that you have to have at least a
> *bad* solution to *all* of the above, to be able to use it at all.  A
> *good* solution still needs to cover *all* the above.  Getting part
> way through and hitting a problem can be very discouraging, but if
> you're up to the challenge, we can point out the specific source files
> you'll need to deal with.
>

You cannot expect that one developer will cover all areas. The common=20
problem with PCB development is that partial or incomplete features are=20
rejected/ignored leading to no progress.

Step-by-step development would be more convenient. Create minimal set=20
features and later improve them. Isn't this essence of "development"?

We can start with easy parts:

1. internal representation. Basically, blind/buried vias  should define=20
the connection from one layer to another. There is only one question to=20
be answered - do we need just single such connection per via or these=20
connections can be stacked (i.e layers 1-2 and layers 4-5-6 are=20
interconnected in one via)? Or enable via stacking (currently not=20
allowed) if they do not overlap? I personally prefer single connection=20
per via and allow via stacking (I feel it more natural).

2. File format - PCB has implemented the  mechanism to identify the=20
minimal required version of file to be saved. If new feature is not=20
used, older format is used. It is implemented for polygon holes already, =

it can be easily extended for blind/buried vias. If no blind/buried vias =

are used, PCB file stays backward compatible.

The features above are easy to implement. In fact, I already did it in=20
last hour (version with single connection per via)

The minimal user interface should consist of:
3. several actions  like SetViaStyle(buried,1-5) or Select(BuriedVias),=20
including undo...
4. object reports (some Ctrl-R report done already).

This minimal set of features does not significantly affect any  part of=20
PCB and does not break any workflow, but IMO creates quite solid=20
playground for developers to implement and test remaining features one=20
by one.

I will try to code the point 3 until mid of next week (I am AFK during=20
weekends) - suggestions are welcome. Points 1,2 and 4 - see patch=20
https://static.bastl.sk/pcb/0001-Burried-vias-step-1.patch.gz

Milan







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