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From:	"Chad Parker (parker DOT charles AT gmail DOT com) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com>
Date:	Mon, 19 Apr 2021 11:23:03 -0400
Message-ID:	<CAJZxidCO0uzA_FfMdfd+WhnrtqGuoStnExxmxWFMLJtacEEBPA@mail.gmail.com>
Subject:	Re: [geda-help] multiple "Joined line/via not connected to polygon"
	errors just appeared...help
To:	geda-help AT delorie DOT com
Reply-To:	geda-help AT delorie DOT com

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Hi Roger-

Sorry for the frustration.

I believe that DRC warning is somewhat recently added. One of the flags
that can be set on many objects is called the "clearline" flag. This flag
is used to indicate that a particular object (line, arc, via) should create
a clearance around itself inside of polygons. If this flag is NOT set, then
that clearance is not created, and the object is electrically connected to
the polygon.

The assumption is that if the clearline flag is NOT set, that the user
wants that particular object to be connected to a polygon. So, DRC checks
to see if that's the case, and if an object does not have the clearline
flag set and is not touching a polygon, it raises a warning. So, in your
case, I would suggest looking at the objects in question and checking these
flags. If you have any objects that are not connected to polygons that also
do not have the clearline flag set, you can set the clearline flag and that
should make the warning go away.

If you've reviewed the area and are confident that the design meets your
requirements, then you can probably ignore those errors. Their primary
purpose is to make sure that pcb did what you intended.

I've worked pretty hard to make sure the DRC works as advertised, but it's
always possible that there's a bug. The whole system is based on a
suboptimal framework that I've been upgrading slowly. If you believe you've
found a bug, it would be very helpful if you could file a bug report or
send me a pcb file that demonstrates the behavior that you believe is an
error.

Thanks,
--Chad

On Sun, Apr 18, 2021 at 3:38 AM Roger Traylor (traylor AT engr DOT orst DOT edu) [via
geda-help AT delorie DOT com] <geda-help AT delorie DOT com> wrote:

> Folks,
>
> Was putting final touches on a design and after some edits now I get
> multiple "joined line/via not connected to polygon" errors. I had been
> increasing the line width of a few traces and little else.
>
> I quit the tool hoping for some resolution as I had seen some errors
> related
> to incorrect serial numbers on undo=E2=80=99s. I saved and restarted as t=
he tool
> advised
> so undoing to get back to square one is not an option.
>
> I have looked at most of the errors flagged. They are all in an area wher=
e
> both top and bottom layers (2.4Ghz, 2 layers) can be used as ground plane=
s.
> Many of the traces have never had a connection to either plane and
> furthermore
> I did not touch them in the final edit session. Others have always been
> connected to the ground plane via a join(on top) followed by a via to bot=
h
> sides
> using thermal tool to connect to both planes.
>
> I think DRC is lying to me. Have looked for hours but cannot find what is
> going on. The only difference in the pieces of the polygons I can find is
> that
> the object report for most is =E2=80=9Cclearly, selected,fullpoly=E2=80=
=9D while one other
> piece
> includes =E2=80=9Cfound=E2=80=9D.  Can someone throw me a idea?
>
> Running PCB 4.2.2 on Ubuntu 19.10.
>
> Thanks in advance,
> Roger Traylor
>

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<div dir=3D"ltr"><div>Hi Roger-</div><div><br></div><div>Sorry for the frus=
tration.=C2=A0</div><div><br></div><div>I believe that DRC warning is somew=
hat recently added. One of the flags that can be set on many objects is cal=
led the &quot;clearline&quot; flag. This flag is used to indicate that a pa=
rticular object (line, arc, via) should create a clearance around itself in=
side of polygons. If this flag is NOT set, then that clearance is not creat=
ed, and the object is electrically connected to the polygon.</div><div><br>=
</div><div>The assumption is that if the clearline flag is NOT set, that th=
e user wants that particular object to be connected to a polygon. So, DRC c=
hecks to see if that&#39;s the case, and if an object does not have the cle=
arline flag set and is not touching a polygon, it raises a warning. So, in =
your case, I would suggest looking at the objects in question and checking =
these flags. If you have any objects that are not connected to polygons tha=
t also do not have the clearline flag set, you can set the clearline flag a=
nd that should make the warning go away.</div><div><br></div><div>If you&#3=
9;ve reviewed the area and are confident that the design meets your require=
ments, then you can probably ignore those errors. Their primary purpose is =
to make sure that pcb did what you intended.<br></div><div><br></div><div>I=
&#39;ve worked pretty hard to make sure the DRC works as advertised, but it=
&#39;s always possible that there&#39;s a bug. The whole system is based on=
 a suboptimal framework that I&#39;ve been upgrading slowly. If you believe=
 you&#39;ve found a bug, it would be very helpful if you could file a bug r=
eport or send me a pcb file that demonstrates the behavior that you believe=
 is an error.<br></div><div><br></div><div>Thanks,</div><div>--Chad<br></di=
v></div><br><div class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr=
">On Sun, Apr 18, 2021 at 3:38 AM Roger Traylor (<a href=3D"mailto:traylor@=
engr.orst.edu">traylor AT engr DOT orst DOT edu</a>) [via <a href=3D"mailto:geda-help@=
delorie.com">geda-help AT delorie DOT com</a>] &lt;<a href=3D"mailto:geda-help AT del=
orie.com">geda-help AT delorie DOT com</a>&gt; wrote:<br></div><blockquote class=
=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-left:1px solid rg=
b(204,204,204);padding-left:1ex">Folks,<br>
<br>
Was putting final touches on a design and after some edits now I get<br>
multiple &quot;joined line/via not connected to polygon&quot; errors. I had=
 been <br>
increasing the line width of a few traces and little else. <br>
<br>
I quit the tool hoping for some resolution as I had seen some errors relate=
d<br>
to incorrect serial numbers on undo=E2=80=99s. I saved and restarted as the=
 tool advised <br>
so undoing to get back to square one is not an option.<br>
<br>
I have looked at most of the errors flagged. They are all in an area where =
<br>
both top and bottom layers (2.4Ghz, 2 layers) can be used as ground planes.=
<br>
Many of the traces have never had a connection to either plane and furtherm=
ore <br>
I did not touch them in the final edit session. Others have always been <br=
>
connected to the ground plane via a join(on top) followed by a via to both =
sides<br>
using thermal tool to connect to both planes.<br>
<br>
I think DRC is lying to me. Have looked for hours but cannot find what is<b=
r>
going on. The only difference in the pieces of the polygons I can find is t=
hat<br>
the object report for most is =E2=80=9Cclearly, selected,fullpoly=E2=80=9D =
while one other piece<br>
includes =E2=80=9Cfound=E2=80=9D.=C2=A0 Can someone throw me a idea? <br>
<br>
Running PCB 4.2.2 on Ubuntu 19.10.<br>
<br>
Thanks in advance,<br>
Roger Traylor<br>
</blockquote></div>

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