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From:	"Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com>
Date:	Sun, 19 Feb 2017 08:27:15 +0000
Message-ID:	<CAJXU7q_327MiNTn7W8ZHFgmhTk7Xf4rxhC_Wawm0vROFHSOadQ@mail.gmail.com>
Subject:	Re: [geda-help] Please help with multiple-pages schematics
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On 19 Feb 2017 04:47, "Vasily Olekhov (olekhov AT gmail DOT com) [via
geda-help AT delorie DOT com]" <geda-help AT delorie DOT com> wrote:

Thank you everyone.
Yes, naming nets that span across the pages helps.

Yet, naming by hand most of QFP144 pins is quite labour-intensive.


Do you need these all to be off page?

Having good netnames is often useful in general, but isn't required if you
can wire up what you need with nets on a particular page.

Whilst as others have pointed out, you can't really use CONN1 on multiple
pages (with the same pins), you certainly CAN split the symbol for a large
component into multiple pieces (all with different pins), and use them in
different places / pages.

This is typically how FPGAs get done, or large system on chip devices where
there are so many pins it is impractical to use a single symbol.

You might have one symbol for the pins on each IO bank, for example.
Another for power. Another for JTAG etc..

At the smaller level, we often do something similar for multiple opamps or
gates in a package. There is a mechanism called "slotting" which lets you
define symbols that change pin number depending upon which device (slot)
number in the chip you are adding to the schematic.  (This is something to
look at later perhaps, once you are happy with the basic parts of the
tools).

Peter C

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<div dir=3D"auto"><div><br><div class=3D"gmail_extra"><br><div class=3D"gma=
il_quote">On 19 Feb 2017 04:47, &quot;Vasily Olekhov (<a href=3D"mailto:ole=
khov AT gmail DOT com">olekhov AT gmail DOT com</a>) [via <a href=3D"mailto:geda-help AT del=
orie.com">geda-help AT delorie DOT com</a>]&quot; &lt;<a href=3D"mailto:geda-help@=
delorie.com">geda-help AT delorie DOT com</a>&gt; wrote:<br type=3D"attribution"><=
blockquote class=3D"quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc =
solid;padding-left:1ex"><div dir=3D"ltr">Thank you everyone.<div>Yes, namin=
g nets that span across the pages helps.</div><div><br></div><div>Yet, nami=
ng by hand most of QFP144 pins is quite labour-intensive.</div></div></bloc=
kquote></div></div></div><div dir=3D"auto"><br></div><div dir=3D"auto">Do y=
ou need these all to be off page?</div><div dir=3D"auto"><br></div><div dir=
=3D"auto">Having good netnames is often useful in general, but isn&#39;t re=
quired if you can wire up what you need with nets on a particular page.</di=
v><div dir=3D"auto"><br></div><div dir=3D"auto">Whilst as others have point=
ed out, you can&#39;t really use CONN1 on multiple pages (with the same pin=
s), you certainly CAN split the symbol for a large component into multiple =
pieces (all with different pins), and use them in different places / pages.=
</div><div dir=3D"auto"><br></div><div dir=3D"auto">This is typically how F=
PGAs get done, or large system on chip devices where there are so many pins=
 it is impractical to use a single symbol.</div><div dir=3D"auto"><br></div=
><div dir=3D"auto">You might have one symbol for the pins on each IO bank, =
for example. Another for power. Another for JTAG etc..</div><div dir=3D"aut=
o"><br></div><div dir=3D"auto">At the smaller level, we often do something =
similar for multiple opamps or gates in a package. There is a mechanism cal=
led &quot;slotting&quot; which lets you define symbols that change pin numb=
er depending upon which device (slot) number in the chip you are adding to =
the schematic. =C2=A0(This is something to look at later perhaps, once you =
are happy with the basic parts of the tools).</div><div dir=3D"auto"><br></=
div><div dir=3D"auto">Peter C</div><div dir=3D"auto"></div><div dir=3D"auto=
"><div class=3D"gmail_extra"><br></div></div></div>

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