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Subject:	Re: [geda-help] pcb: blind via
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From:	"Milan Prochac (milan AT prochac DOT sk) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com>
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To close this topic:

The implementation is finished for several months already, just some=20
details are missing (like special naming convention should be extended=20
to cover blind/buried vias). But I lost any motivation to participate on =

this dead project, so these minor enhancements are not implemented,=20
including some more "planned" enhancements like layer-pair definition=20
according fab requirements (and new DRC checks to enforce them),=20
restrict layer grouping to continuous groups (non-continuous groups are=20
confusing in combination with blind/buried vias) and handling of via=20
endpoints when line segment is moved.

I finally decided to provide existing version as is - it should be fully =

working, it just needs more public testing and feedback. Here:=20
https://bugs.launchpad.net/pcb/+bug/1656661

If no blind/buried via is used and no specific option is turned on, file =

format is backwards compatible.

I found that there was already created another implementation - in 2008=20
- and it was not touched on launchpad  until 2015...

So see you in 2024.

Milan


On 24.08.2016 14:26, Milan Prochac (milan AT prochac DOT sk) [via=20
geda-help AT delorie DOT com] wrote:
>
> Status update, to keep the topic warm:
>
> * visual presentation:
>   - blind/buried vias have 2 half-circles drawn on top; colors=20
> indicate starting and ending layer of blind/buried via=20
> (https://static.bastl.sk/pcb/bvias_01.png)
>   - if all layers penetrated by blind/buried via are turned off the=20
> via is thin-drawn (https://static.bastl.sk/pcb/bvias_02.png)
>
> * action to set blind/buried vias was modified to allow set only one=20
> end and use currently active layer; such actions can be bound to menu=20
> items and hot-keys (done for GTK HID) -=20
> https://static.bastl.sk/pcb/bvias_03.png and=20
> https://static.bastl.sk/pcb/bvias_04.png. These actions together with=20
> visualisation and immediate on-screen changes seems to be sufficient=20
> user interface, so no GUI dialog will be implemented.
>
> * Ratnest optimization and short detection was modified to take=20
> blind/buried into account
>
> * Layer management is partially done - adding and removing layer works =

> fine, moving layer is not completely finished/tested.
>
> * When layer is changed during line draw, the automatically created=20
> vias can be blind/buried; the same applies for line move from one=20
> layer to another. This behavior is controlled by option=20
> (https://static.bastl.sk/pcb/bvias_06.png). On following pictures the=20
> identical operation was first performed with option switched off=20
> (upper track) and with option switched on; line draw:=20
> https://static.bastl.sk/pcb/bvias_04.png and line move:=20
> https://static.bastl.sk/pcb/bvias_05.png. The via creation logic was=20
> not changed, only via type is affected.
>
> * export hid was adjusted to create additional drill layers for layer=20
> pairs connected by blind/buried vias. The default drill layer is used=20
> for through-hole pins and vias - if no blind/buried vias are used,=20
> there is no change in generated output.
>   - no changes in exporter API; backward compatibility with external=20
> exporters is retained
>   - PS and Gerber exporters were modified to accept additional layers=20
> - the only change was the filename creation (plus font size and line=20
> spacing on TOC page of PS export); for gerber the alternate naming=20
> schemes need to be adjusted.
>   - remaining standard exporters need to be reviewed, but at first=20
> look they do not need any change; the OpenSCAD exporter will be=20
> adjusted later.
>
> There are still some minor issues - for example freedom in layer=20
> grouping: if layer group does not contain contiguous layers, the=20
> behavior is confusing (but correct) in some situations. I need to=20
> decide the level of warnings about this situation or enforcing the=20
> contiguous layer groups.
>
> Another one are degraded vias (single layer vias). Vias with both ends =

> on the same layer can be avoided (and automatically deleted after=20
> layer removal for example), but vias with both ends on same layer=20
> group cannot be avoided easily. Behavior is correct, just unnecessary=20
> copper ring with no associated drill is created on respective layer=20
> group.  Maybe these degraded vias should be detected as part of DRC.
>
> The special topic is the output used for PCB fabrication. Currently=20
> the drill pairs are automatically generated. Maybe  some kind of drill =

> pair configuration and checks if design fits these pairs should be=20
> implemented. I have very little experience with commercial packages=20
> (and no time to learn them), so some feedback or ideas are welcome.
>
> Milan
>
>
>
> On 8/3/2016 3:31 AM, Milan Prochac (milan AT prochac DOT sk) [via=20
> geda-help AT delorie DOT com] wrote:
>>
>> Update:
>>
>> Already implemented:
>>   1. internal representation. Single connection per via is=20
>> implemented. Via stacking will be enabled later.
>>   2. file format with backward compatibility (if no blind/buried vias =

>> are used); bugs fixed
>>   3. new action SetViaLayers implemented. Select action extended by=20
>> BuriedVias parameter. See generated pcb.pdf for more details
>>       3a. Undo was extended to cover new operations
>>   4. object report (Ctrl-R) contains information about blind/buried vi=
as
>>   5. Drawing code updated:
>>       5a. on GUI HID (screen) vias themselves are drawn unchanged.=20
>> Any recommendation how to visually distinguish blind/buriad vias from =

>> through-hole vias are welcome.
>>       5b. on GUI HID (screen) clerarances and thermals are cut-out=20
>> only on respective layers
>>       5c. on non-GUI HID exporters both vias and clearances/thermals=20
>> are drawn on respective layers only
>>   6. exporters which use standard drawing interface displays correct=20
>> data (tested on PostScript and gerber). Drill information will=20
>> require serious reworking - single plated and unplated drill is not=20
>> sufficient;
>>
>> What will come next
>>   7. ERC check (optimize rats) to evaluate connections only on proper =

>> layers
>>   8. maintain layer information after layer operations: new layer,=20
>> remove layer, move layer
>>   9. maintain layer information after line move to another layer
>> 10. automatically create blind/buried via when changed layer during=20
>> line drawing; it will be controlled by option.
>> 11. update solder mask drawing
>> 12. GUI dialog to change via type
>>
>> Current code: https://static.bastl.sk/pcb/Burried-vias-step-2.tar.gz=20
>> . Testers are welcome.
>>
>> Milan
>>
>>
>
>



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