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Subject:	Re: [geda-help] pcb: blind via
To:	geda-help AT delorie DOT com
References:	<20160728160657 DOT 7f68f787 AT debian>
	<20160728174027 DOT 453b2b41 AT debian DOT olsr> <20160728192015 DOT 4fc84ce8 AT debian DOT olsr>
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	<f3e69165-857d-c541-33d1-557fc93172a4 AT prochac DOT sk>
	<b7127584-363e-2903-3382-8ba0eda2c02d AT prochac DOT sk>
From:	"Milan Prochac (milan AT prochac DOT sk) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com>
Message-ID:	<39718d63-9fb1-3cd0-bcfd-32c60e0255ef@prochac.sk>
Date:	Wed, 24 Aug 2016 14:26:20 +0200
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Status update, to keep the topic warm:

* visual presentation:
   - blind/buried vias have 2 half-circles drawn on top; colors indicate =

starting and ending layer of blind/buried via=20
(https://static.bastl.sk/pcb/bvias_01.png)
   - if all layers penetrated by blind/buried via are turned off the via =

is thin-drawn (https://static.bastl.sk/pcb/bvias_02.png)

* action to set blind/buried vias was modified to allow set only one end =

and use currently active layer; such actions can be bound to menu items=20
and hot-keys (done for GTK HID) -=20
https://static.bastl.sk/pcb/bvias_03.png and=20
https://static.bastl.sk/pcb/bvias_04.png. These actions together with=20
visualisation and immediate on-screen changes seems to be sufficient=20
user interface, so no GUI dialog will be implemented.

* Ratnest optimization and short detection was modified to take=20
blind/buried into account

* Layer management is partially done - adding and removing layer works=20
fine, moving layer is not completely finished/tested.

* When layer is changed during line draw, the automatically created vias =

can be blind/buried; the same applies for line move from one layer to=20
another. This behavior is controlled by option=20
(https://static.bastl.sk/pcb/bvias_06.png). On following pictures the=20
identical operation was first performed with option switched off (upper=20
track) and with option switched on; line draw:=20
https://static.bastl.sk/pcb/bvias_04.png and line move:=20
https://static.bastl.sk/pcb/bvias_05.png. The via creation logic was not =

changed, only via type is affected.

* export hid was adjusted to create additional drill layers for layer=20
pairs connected by blind/buried vias. The default drill layer is used=20
for through-hole pins and vias - if no blind/buried vias are used, there =

is no change in generated output.
   - no changes in exporter API; backward compatibility with external=20
exporters is retained
   - PS and Gerber exporters were modified to accept additional layers - =

the only change was the filename creation (plus font size and line=20
spacing on TOC page of PS export); for gerber the alternate naming=20
schemes need to be adjusted.
   - remaining standard exporters need to be reviewed, but at first look =

they do not need any change; the OpenSCAD exporter will be adjusted later=
=2E

There are still some minor issues - for example freedom in layer=20
grouping: if layer group does not contain contiguous layers, the=20
behavior is confusing (but correct) in some situations. I need to decide =

the level of warnings about this situation or enforcing the contiguous=20
layer groups.

Another one are degraded vias (single layer vias). Vias with both ends=20
on the same layer can be avoided (and automatically deleted after layer=20
removal for example), but vias with both ends on same layer group cannot =

be avoided easily. Behavior is correct, just unnecessary copper ring=20
with no associated drill is created on respective layer group.  Maybe=20
these degraded vias should be detected as part of DRC.

The special topic is the output used for PCB fabrication. Currently the=20
drill pairs are automatically generated. Maybe  some kind of drill pair=20
configuration and checks if design fits these pairs should be=20
implemented. I have very little experience with commercial packages (and =

no time to learn them), so some feedback or ideas are welcome.

Milan



On 8/3/2016 3:31 AM, Milan Prochac (milan AT prochac DOT sk) [via=20
geda-help AT delorie DOT com] wrote:
>
> Update:
>
> Already implemented:
>   1. internal representation. Single connection per via is=20
> implemented. Via stacking will be enabled later.
>   2. file format with backward compatibility (if no blind/buried vias=20
> are used); bugs fixed
>   3. new action SetViaLayers implemented. Select action extended by=20
> BuriedVias parameter. See generated pcb.pdf for more details
>       3a. Undo was extended to cover new operations
>   4. object report (Ctrl-R) contains information about blind/buried via=
s
>   5. Drawing code updated:
>       5a. on GUI HID (screen) vias themselves are drawn unchanged. Any =

> recommendation how to visually distinguish blind/buriad vias from=20
> through-hole vias are welcome.
>       5b. on GUI HID (screen) clerarances and thermals are cut-out=20
> only on respective layers
>       5c. on non-GUI HID exporters both vias and clearances/thermals=20
> are drawn on respective layers only
>   6. exporters which use standard drawing interface displays correct=20
> data (tested on PostScript and gerber). Drill information will require =

> serious reworking - single plated and unplated drill is not sufficient;=

>
> What will come next
>   7. ERC check (optimize rats) to evaluate connections only on proper=20
> layers
>   8. maintain layer information after layer operations: new layer,=20
> remove layer, move layer
>   9. maintain layer information after line move to another layer
> 10. automatically create blind/buried via when changed layer during=20
> line drawing; it will be controlled by option.
> 11. update solder mask drawing
> 12. GUI dialog to change via type
>
> Current code: https://static.bastl.sk/pcb/Burried-vias-step-2.tar.gz . =

> Testers are welcome.
>
> Milan
>
>



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