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Date:	Mon, 27 Jul 2015 14:28:31 +0200
Message-ID:	<CAONhAosde+B+LW5RcmYGgved5ndE-9qbL5Ptvxh1EneHoHsB8A@mail.gmail.com>
Subject:	Re: [geda-help] Strategy of adding netname attributes in gSchem?
From:	"=?UTF-8?B?Q3PDoW55aSBQw6Fs?= (csanyipal AT gmail DOT com) [via geda-help AT delorie DOT com]" <geda-help AT delorie DOT com>
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Hello Robert,

2015-07-27 12:24 GMT+02:00 myken <myken AT iae DOT nl>:

> Please take an other look at your schematics.
> All nets with the same name will be tied together. Looking at your schematic
> I see two nets with the name C and two nets with the name Q that probably
> shouldn't be connected to each-other.
> So net C connected to pin 1 of U1 will be short-circuit to net C connected
> to pin 3 of U1, is that what you want?

No.
I did take a look at mine schematic again and I understand now what to do.
My schematic with changed netnames:

v 20130925 2
C 40000 40000 0 0 0 title-B.sym
T 41300 40100 9 20 1 0 0 0 1
Környezetkímélő szúnyogriasztó
T 55400 40200 9 10 1 0 0 0 1
Csányi Pál
T 51900 40200 9 10 1 0 0 0 1
BiG
C 49900 44000 1 0 0 4047-1.sym
{
T 50200 47050 5 10 0 0 0 0 1
device=4047
T 50200 47250 5 10 0 0 0 0 1
footprint=DIP14
T 51500 46900 5 10 1 1 0 6 1
refdes=U1
T 49900 44000 5 10 0 0 0 0 1
footprint=DIP14
T 50200 48050 5 10 0 0 0 0 1
documentation=http://www.semiconductors.philips.com/acrobat/datasheets/HEF4047B_CNV_3.pdf
T 50200 47150 5 10 1 0 0 0 1
net=VDD:14
T 50200 47350 5 10 1 0 0 0 1
net=VSS:7
}
C 52800 45000 1 90 0 beeper-1.sym
{
T 51900 45300 5 10 0 0 90 0 1
device=BEEPER
T 52100 45300 5 10 1 1 90 0 1
refdes=U2
T 51700 45300 5 10 0 0 90 0 1
symversion=0.1
T 52800 45000 5 10 1 1 0 0 4
description=Piezo hangszóró
PCT, 90 dB,
2,83 V(RMS),
2,5-60 kHz
T 52800 45000 5 10 0 0 0 0 1
footprint=CONNECTOR 1 2
}
C 51800 46200 1 0 0 nc-right-1.sym
{
T 51900 46700 5 10 0 0 0 0 1
value=NoConnection
T 51900 46900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 46300 47000 1 90 1 battery-3.sym
{
T 45600 46700 5 10 0 0 270 2 1
device=BATTERY
T 45800 46700 5 10 1 1 270 2 1
refdes=B1
T 45350 46700 5 10 0 0 270 2 1
symversion=0.1
T 45600 47000 5 10 1 1 0 0 1
value=9V
T 46300 47000 5 10 0 0 0 0 1
footprint=CONNECTOR 1 2
T 46300 47000 5 10 0 0 0 0 1
net=VDD:1
T 46300 47000 5 10 0 0 0 0 1
net=VSS:2
}
C 48000 44200 1 0 0 gnd-1.sym
C 49000 46200 1 0 0 resistor-2.sym
{
T 49400 46550 5 10 0 0 0 0 1
device=RESISTOR
T 49200 46500 5 10 1 1 0 0 1
refdes=R1
T 49200 46100 5 10 1 1 0 0 1
value=1K3
T 49000 46200 5 10 0 0 0 0 1
footprint=ACY400
}
C 48100 46200 1 0 0 pot-bourns.sym
{
T 48900 47100 5 10 0 0 0 0 1
device=VARIABLE_RESISTOR
T 48700 46600 5 10 1 1 0 0 1
refdes=P1
T 48400 46100 5 10 1 1 0 0 1
value=2K5
T 48100 46200 5 10 0 0 0 0 1
footprint=BOURNS_3224J
}
C 47100 46900 1 90 1 capacitor-4.sym
{
T 46000 46700 5 10 0 0 270 2 1
device=POLARIZED_CAPACITOR
T 46600 46700 5 10 1 1 270 2 1
refdes=C3
T 46400 46700 5 10 0 0 270 2 1
symversion=0.1
T 46500 46300 5 10 1 1 270 0 1
value=100u 15V
T 47100 46900 5 10 0 0 0 0 1
footprint=RCY100P
}
C 47900 46000 1 90 0 capacitor-1.sym
{
T 47200 46200 5 10 0 0 90 0 1
device=CAPACITOR
T 47400 46200 5 10 1 1 90 0 1
refdes=C1
T 47000 46200 5 10 0 0 90 0 1
symversion=0.1
T 47400 46500 5 10 1 1 90 0 1
value=4n7
T 47900 46000 5 10 0 0 0 0 1
footprint=ACY100
}
C 46100 48300 1 0 0 switch-spst-1.sym
{
T 46500 49000 5 10 0 0 0 0 1
device=SPST
T 46400 48600 5 10 1 1 0 0 1
refdes=S1
T 46100 48300 5 10 0 0 0 0 1
footprint=CONNECTOR 1 2
}
N 47700 46000 49900 46000 4
N 48600 46800 48100 46800 4
N 48100 46000 48100 46800 4
N 52500 46000 51800 46000 4
N 51800 46000 51800 45700 4
N 52500 45000 51800 45000 4
N 51800 45000 51800 45300 4
N 46900 48300 47200 48300 4
N 46900 48300 46900 46900 4
N 47200 48300 47200 45400 4
N 47200 45400 49900 45400 4
N 49900 45100 49900 45700 4
N 46900 46000 46900 44500 4
N 46100 44500 49900 44500 4
N 49900 44200 49900 44800 4
N 46100 48300 46100 47000 4
N 46100 45900 46100 44500 4
C 47900 46900 1 90 0 capacitor-1.sym
{
T 47200 47100 5 10 0 0 90 0 1
device=CAPACITOR
T 47400 47100 5 10 1 1 90 0 1
refdes=C2
T 47000 47100 5 10 0 0 90 0 1
symversion=0.1
T 47400 47400 5 10 1 1 90 0 1
value=8n2
T 47900 46900 5 10 0 0 0 0 1
footprint=ACY100
}
N 47700 47800 49900 47800 4
N 49900 47800 49900 46600 4

I get a fine pcb layout from this schematics abowe.
I wanted to share the pcb file here but it is very long to paste it here.
Can I attach it here?

-- 
Regards from Pál

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