Mail Archives: geda-help/2014/10/08/12:49:07
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| Date: | Wed, 8 Oct 2014 16:48:51 +0000 (UTC)
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| From: | Jason McLafferty <jason1391978 AT yahoo DOT com>
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| To: | "geda-help AT delorie DOT com" <geda-help AT delorie DOT com>
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| In-Reply-To: | <1412784061.2815.98.camel@linetec>
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| Subject: | Re: [geda-help] Panelizing howto or examples?
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------=_Part_1106922_2126294198.1412786931328
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Hi Richard,
I have panelized boards that I later separate myself.=C2=A0 To do this, I d=
raw a line on the top silk layer so I know where I want to cut the boards.
Here is the approach I have used to do this in pcb:(1) Make sure settings -=
> "Require Unique Element Names" is NOT selected.=C2=A0 This makes sure eac=
h copy of the board on the panel has the same part number for each part.=C2=
=A0 Otherwise, for example, R1 on the original board becomes R(some other n=
umber) on the next copy on the panel.(2) Figure out what size the overall p=
anelized board is going to be, being sure to allow for kerf for separating =
the boards plus any extra you want.
(3) Resize the board according to what you come up with in step (2) (File -=
> Preferences, sizes on left side).(4) To align boards for pasting the layo=
ut, I draw lines:(a) I draw lines on the OUTLINE layer to start (you'll see=
why...)=C2=A0 I place these lines where I want the edge of the copies of t=
he original board to end up as I panelize.(c) Say I want to lay out the pan=
el as a row of boards.=C2=A0 I drop the measurement origin (CTRL + m) on th=
e top right corner of my original board.=C2=A0 The I use the coordinates to=
go the proper horizontal distance (the kerf plus any extra spacing).=C2=A0=
This is left edge of next board on panel.(d) Now I draw a vertical line on=
the OUTLINE layer.(e) Next, de-select the OUTLINE layer (so it is invisibl=
e).(5) Mouse over the center of the original board.(6) ALT-a selects all la=
yers of the original board.(7) CTRL - C copies all layers to a buffer.(8) N=
ow, turn back on OUTLINE layer.=C2=A0 The line indicating the left edge of =
the new board re-appears.(9) Click on the copied layers (original board - I=
think it changes to light blue when it has been copied to buffer IIRC).(10=
) Drag the copy to the right until the left edge of the copied board is cen=
tered on the OUTLINE layer that you drew to indicate the placement of the l=
eft edge of board.(11) Repeat steps until you have all copies of board plac=
ed on panelized board.(12) Now, convert the OUTLINE board edges to SILK lin=
es.=C2=A0 The board house I use only wants one outline, for the entire boar=
d.=C2=A0 By using SILK lines, they will show up and I know where to cut.(a)=
Trace the OUTLINE board edges in SILK lines.(b) Turn off SILK layer so the=
original OUTLINE lines are visible.(c) Delete these OUTLINE lines so the b=
oard manufacturer is not confused where the outline layer is.(d) Now make s=
ure the panelized board has its outline draw on the OUTLINE layer.
That should be all the steps.=C2=A0 Of course, I usually save a lot of inte=
rmediate files during the process in case I make a mistake and need to reve=
rt.
Hope this helps!
Jason
=20
On Wednesday, October 8, 2014 12:01 PM, Richard Rasker <rasker AT linetec=
.nl> wrote:
=20
Hello,
I've got a small PCB (38 mm x 21.4 mm, 12 components) that I'm trying to
panelize. The idea is to use a a routed outline that is connected to the
panel by its two right-hand corners -- see attached PCB file for an
example.
I simply created breaks in the outline, copied the single PCB, and drew
a new outline around the panel (the actual panel will be somewhat
larger, of course -- this is my first attempt at panelizing).
However, when I upload the exported Gerber files to my usual PCB
manufacturer (Eurocircuits) and have it analyzed, I get an error about
an unrecognized file format. I think that their analysis tools are
confused by non-closed and nested outlines.
I also found a reference to DJ Delorie's panelize plug-ins for PCB, but
I have no clue how to actually 'plug these in' in PCB -- I have
Mehanik's repository active, but the pcb-plugins package is not found.=20
Also, I assume that it should be a simple matter of copying PCB's and
perhaps juggle outlines and/or add some layer or other.
Or is panelizing something not done within PCB?
Of course I can simply tell the manufacturer to panelize these for me,
but then the cutting points can end up anywhere, which makes for a lot
of fiddly machining afterwards.
Is there a simple explanation somewhere, and/or perhaps some example
files?
Thank you in advance,
Best regards,
Richard Rasker
------=_Part_1106922_2126294198.1412786931328
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
<html><body><div style=3D"color:#000; background-color:#fff; font-family:He=
lveticaNeue, Helvetica Neue, Helvetica, Arial, Lucida Grande, sans-serif;fo=
nt-size:16px"><div id=3D"yui_3_16_0_1_1412785754232_4560">Hi Richard,</div>=
<div id=3D"yui_3_16_0_1_1412785754232_4573"><br></div><div id=3D"yui_3_16_0=
_1_1412785754232_4574" dir=3D"ltr">I have panelized boards that I later sep=
arate myself. To do this, I draw a line on the top silk layer so I kn=
ow where I want to cut the boards.</div><div id=3D"yui_3_16_0_1_14127857542=
32_4585" dir=3D"ltr"><br></div><div id=3D"yui_3_16_0_1_1412785754232_4592" =
dir=3D"ltr">Here is the approach I have used to do this in pcb:</div><div i=
d=3D"yui_3_16_0_1_1412785754232_4597" dir=3D"ltr">(1) Make sure settings -&=
gt; "Require Unique Element Names" is NOT selected. This makes sure e=
ach copy of the board on the panel has the same part number for each part.&=
nbsp; Otherwise, for example, R1 on the original board becomes R(some other=
number) on the next copy on the panel.</div><div id=3D"yui_3_16_0_1_141278=
5754232_4625" dir=3D"ltr">(2) Figure out what size the overall panelized bo=
ard is going to be, being sure to allow for kerf for separating the boards =
plus any extra you want.<br></div><div id=3D"yui_3_16_0_1_1412785754232_462=
8" dir=3D"ltr">(3) Resize the board according to what you come up with in s=
tep (2) (File -> Preferences, sizes on left side).</div><div id=3D"yui_3=
_16_0_1_1412785754232_4629" dir=3D"ltr">(4) To align boards for pasting the=
layout, I draw lines:</div><div id=3D"yui_3_16_0_1_1412785754232_4660" dir=
=3D"ltr">(a) I draw lines on the OUTLINE layer to start (you'll see why...)=
I place these lines where I want the edge of the copies of the origi=
nal board to end up as I panelize.</div><div id=3D"yui_3_16_0_1_14127857542=
32_4666" dir=3D"ltr">(c) Say I want to lay out the panel as a row of boards=
. I drop the measurement origin (CTRL + m) on the top right corner of=
my original board. The I use the coordinates to go the proper horizo=
ntal distance (the kerf plus any extra spacing). This is left edge of=
next board on panel.</div><div id=3D"yui_3_16_0_1_1412785754232_4816" dir=
=3D"ltr">(d) Now I draw a vertical line on the OUTLINE layer.</div><div id=
=3D"yui_3_16_0_1_1412785754232_4821" dir=3D"ltr">(e) Next, de-select the OU=
TLINE layer (so it is invisible).</div><div id=3D"yui_3_16_0_1_141278575423=
2_4830" dir=3D"ltr">(5) Mouse over the center of the original board.</div><=
div id=3D"yui_3_16_0_1_1412785754232_4832" dir=3D"ltr">(6) ALT-a selects al=
l layers of the original board.</div><div id=3D"yui_3_16_0_1_1412785754232_=
4837" dir=3D"ltr">(7) CTRL - C copies all layers to a buffer.</div><div id=
=3D"yui_3_16_0_1_1412785754232_5412" dir=3D"ltr">(8) Now, turn back on OUTL=
INE layer. The line indicating the left edge of the new board re-appe=
ars.</div><div id=3D"yui_3_16_0_1_1412785754232_4854" dir=3D"ltr">(9) Click=
on the copied layers (original board - I think it changes to light blue wh=
en it has been copied to buffer IIRC).</div><div id=3D"yui_3_16_0_1_1412785=
754232_4855" dir=3D"ltr">(10) Drag the copy to the right until the left edg=
e of the copied board is centered on the OUTLINE layer that you drew to ind=
icate the placement of the left edge of board.</div><div id=3D"yui_3_16_0_1=
_1412785754232_4864" dir=3D"ltr">(11) Repeat steps until you have all copie=
s of board placed on panelized board.</div><div id=3D"yui_3_16_0_1_14127857=
54232_4873" dir=3D"ltr">(12) Now, convert the OUTLINE board edges to SILK l=
ines. The board house I use only wants one outline, for the entire bo=
ard. By using SILK lines, they will show up and I know where to cut.<=
/div><div id=3D"yui_3_16_0_1_1412785754232_4890" dir=3D"ltr">(a) Trace the =
OUTLINE board edges in SILK lines.</div><div id=3D"yui_3_16_0_1_14127857542=
32_4897" dir=3D"ltr">(b) Turn off SILK layer so the original OUTLINE lines =
are visible.</div><div id=3D"yui_3_16_0_1_1412785754232_4898" dir=3D"ltr">(=
c) Delete these OUTLINE lines so the board manufacturer is not confused whe=
re the outline layer is.</div><div id=3D"yui_3_16_0_1_1412785754232_5419" d=
ir=3D"ltr">(d) Now make sure the panelized board has its outline draw on th=
e OUTLINE layer.</div><div dir=3D"ltr"><br></div><div id=3D"yui_3_16_0_1_14=
12785754232_5430" dir=3D"ltr">That should be all the steps. Of course=
, I usually save a lot of intermediate files during the process in case I m=
ake a mistake and need to revert.</div><div id=3D"yui_3_16_0_1_141278575423=
2_5431" dir=3D"ltr"><br></div><div id=3D"yui_3_16_0_1_1412785754232_5432" d=
ir=3D"ltr">Hope this helps!</div><div id=3D"yui_3_16_0_1_1412785754232_5433=
" dir=3D"ltr"><br></div><div id=3D"yui_3_16_0_1_1412785754232_5434" dir=3D"=
ltr">Jason<br></div><div id=3D"yui_3_16_0_1_1412785754232_4559"><span></spa=
n></div> <div class=3D"qtdSeparateBR"><br><br></div><div style=3D"display: =
block;" class=3D"yahoo_quoted"> <div style=3D"font-family: HelveticaNeue, H=
elvetica Neue, Helvetica, Arial, Lucida Grande, sans-serif; font-size: 16px=
;"> <div style=3D"font-family: HelveticaNeue, Helvetica Neue, Helvetica, Ar=
ial, Lucida Grande, sans-serif; font-size: 16px;"> <div dir=3D"ltr"> <font =
size=3D"2" face=3D"Arial"> On Wednesday, October 8, 2014 12:01 PM, Richard =
Rasker <rasker AT linetec DOT nl> wrote:<br> </font> </div> <br><br> <div c=
lass=3D"y_msg_container">Hello,<br><br>I've got a small PCB (38 mm x 21.4 m=
m, 12 components) that I'm trying to<br>panelize. The idea is to use a a ro=
uted outline that is connected to the<br>panel by its two right-hand corner=
s -- see attached PCB file for an<br>example.<br><br>I simply created break=
s in the outline, copied the single PCB, and drew<br>a new outline around t=
he panel (the actual panel will be somewhat<br>larger, of course -- this is=
my first attempt at panelizing).<br><br>However, when I upload the exporte=
d Gerber files to my usual PCB<br>manufacturer (Eurocircuits) and have it a=
nalyzed, I get an error about<br>an unrecognized file format. I think that =
their analysis tools are<br>confused by non-closed and nested outlines.<br>=
<br>I also found a reference to DJ Delorie's panelize plug-ins for PCB, but=
<br>I have no clue how to actually 'plug these in' in PCB -- I have<br>Meha=
nik's repository active, but the pcb-plugins package is not found. <br>Also=
, I assume that it should be a simple matter of copying PCB's and<br>perhap=
s juggle outlines and/or add some layer or other.<br>Or is panelizing somet=
hing not done within PCB?<br><br>Of course I can simply tell the manufactur=
er to panelize these for me,<br>but then the cutting points can end up anyw=
here, which makes for a lot<br>of fiddly machining afterwards.<br><br>Is th=
ere a simple explanation somewhere, and/or perhaps some example<br>files?<b=
r><br>Thank you in advance,<br><br>Best regards,<br><br>Richard Rasker<br><=
br><br></div> </div> </div> </div> </div></body></html>
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