Mail Archives: geda-help/2011/10/16/17:00:31
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On Sun, 2011-10-16 at 21:53 +0200, Richard Rasker wrote:
> Hello,
>=20
> I'm busy with a design incorporating DDR RAM chips, where signal timing
> and hence line length is of the essence.
As a related question, when you have curved or stepped traces - how does
the effective electrical length compare to the actual track geometry?=20
For example, a curved trace is shorter along its inner edge than on its
centreline. Does this mean we should count the shortest possible
"rubber-band" path within the actual track, or does the radiation
pattern push the current to the centre of the track?
Are these effects significant enough to worry about?
How tight to you have to match the track lengths on a modern DDR chip?
Does track inductance / capacitance to surroundings create a more
significant delay effect?
> I already defined a key binding for reporting net length, and now I
> found that the mil/mm rounding error sometimes causes problems in an
> insidious way: when an extra "mini-line" (dot) is created at a via or
> bend point, and this point is subsequently dragged along the line
> itself, the dot gets stretched into a line.
> I don't always notice when this happens, and the problem is that the
> length of the inadvertently created line is added to the total line
> length. Worst case, I end up with quite the wrong length.
>=20
> Is there an easy way to find or eliminate these dot/lines?
I believe DJ might have had have a plugin for finding and eliminating
short track segments, but I may also have just made that up. Finding the
very short segments is probably easier than once they have been
stretched of course.
I'm not certain whether these short stub tracks should be created since
we moved to nm internal units. If they are - perhaps the underlying
cause was not as we thought, and is still lurking.
What PCB version are you using?
Best wishes,
Peter Clifton
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