Mail Archives: geda-help/2011/10/16/15:53:40
Hello,
I'm busy with a design incorporating DDR RAM chips, where signal timing
and hence line length is of the essence.
I already defined a key binding for reporting net length, and now I
found that the mil/mm rounding error sometimes causes problems in an
insidious way: when an extra "mini-line" (dot) is created at a via or
bend point, and this point is subsequently dragged along the line
itself, the dot gets stretched into a line.
I don't always notice when this happens, and the problem is that the
length of the inadvertently created line is added to the total line
length. Worst case, I end up with quite the wrong length.
Is there an easy way to find or eliminate these dot/lines?
Thanks in advance,
Best regards,
Richard Rasker
- Raw text -