Mail Archives: djgpp/2009/05/05/01:17:02

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From: Rugxulo <rugxulo AT gmail DOT com>
Newsgroups: comp.os.msdos.djgpp
Subject: Re: Please help resurrecting GDB for version 7.0 release
Date: Mon, 4 May 2009 22:08:44 -0700 (PDT)
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On May 4, 10:10=A0pm, Eli Zaretskii <e DOT  DOT  DOT  AT gnu DOT org> wrote:
> > From: Rugxulo <rugx DOT  DOT  DOT  AT gmail DOT com>
> > Date: Mon, 4 May 2009 15:07:21 -0700 (PDT)
> > > As Charles points out, adding
> > > SSE support will need code added to determine whether FXSAVE/FXRSTOR
> > > are supported before we use them, and a lot of testing to make sure w=
> > > don't break old machines.
> > 1). See if CPUID supported (bit 21 of eflags)
> > 2). See if FXSAVE / FXRSTOR supported (bit 24 of edx result from cpuid
> > eax=3D1)
> > 3). See if SSE supported (SSE1 is bit 25 of edx result from cpuid
> > eax=3D1, SSE2 is bit 26, SSE3 is bit 0 of ecx)
> > 4). If not already using CWSDPMI r5 2008, set bit 9 (OSFXSR) of CR4
> > and turn off bit 2 of CR0 (EM - emulation) -- typically done in ring
> > 0, but some ring 3 environments emulate it for you (JEMM386)
> Yes, and then test a lot on old machines which I don't even know where
> to find. =A0

What old machines in particular? Just cpu revisions or OSes or both??
I know that not all 486s support CPUID (e.g. my old 486 Sx/25 doesn't;
also DOSBox supports it in its 486/DX2 but doesn't report it correctly
via eflags). As mentioned, also not all PIIs lack FXSAVE / FXRSTOR
(surprisingly). SSE2 first came about in Intel P4s (and later Pentium-
M, aka PIII + SSE2) and AMD64 (I have a working P4 XP desktop and an
AMD64 Vista laptop.)

WinXP won't let you read or write to CRx registers, apparently, but
WinME didn't seem to mind in my brief testing (although I don't have
access to that anymore). But that cpu didn't support SSE2 anyways, so
I couldn't 100% test, but my attempts writing to CR0 and/or CR4 didn't
seem to cause any noticeable difference (via a silly WDOSX test .EXE).
DOSEMU 1.4.0 (ring 3) doesn't let you read / write to CRx, but WINE
1.01 (ring 0??) doesn't mind. In other words, it's probably not a good
idea to enable SSE unless in ring 0 unless you're absolutely certain
it's allowed.

In other words, I would've thought you could do the following in ring
3, but apparently not:

  mov eax,cr4                ; (CR4 first introduced in Pentium)
  bt eax,OSFXSR              ; if already set, no need to enable
  jc .bye

> All this just to have a change in a version that isn't going
> to be released any time soon? =A0Doesn't sound like a good investment of
> my scarce resources.
> > > OTOH, if someone needs it badly on a machine that is known to support
> > > these instructions, they can simply replace FNSAVE/FRSTOR with the
> > > extended instructions, modify the definition of the NPX object in
> > > debug/dbgcom.h to accommodate for the extra registers, and be done.
> > You make it sound trivial, not sure it is.
> It's trivial. =A0You can try it.

FXSAVE / FXRSTOR use a 512-byte buffer, but not all of that is used (I
think), esp. if SSE is not already enabled (which is how Agner Fog
claims Intel told him to know whether it is enabled ... see if it
saves / restores the SSE "xmm0" etc. registers.).

Did any of that help? I hope I explained / understood it correctly!

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