From:	Jason Green <news AT jgreen4 DOT fsnet DOT co DOT uk>
To:	djgpp AT delorie DOT com
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: Make file wildcards
Date:	Sat, 24 Jun 2000 18:39:32 +0100
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"Eli Zaretskii" <eliz AT is DOT elta DOT co DOT il> wrote:

> > Sorry, I still don't get it.  I understand your original reply to mean
> > that there are cases where a built-in implicit rule takes precedence
> > over an implicit rule defined in the makefile.
> 
> With implicit rules, there's no precedence.  You can have several
> different implicit rules that can be applied to create the same
> target.  Make will choose one of them, but not necessarily the last
> one it sees.

But there is some method in its madness. ;-)

> > Can you give an example of this (if you really mean that)?
> 
> What's wrong with the example which started this thread?

Only that you said that it

> is just another implicit rule, not unlike the one that Make already
> knows about.  When Make sees more than one implicit rule to build the
> same target, it chooses the first one, which will always be the one
> that's built into Make.

Which got me confused because the makefile rule and the built-in are
not alike, and I would expect make to always prefer a makefile rule
over any built-in.  Please do correct me if I am wrong.

> The original makefile *did* include a rule to produce foo.o given
> foo.cpp.  And that is what important, as far as Make is concerned.

Ok, slight technicality. ;-) This rule:

%.o : %.c %.cpp %.h
	$(CC) $(CFLAGS) -c $<

will produce test.o given test.c *and* test.cpp *and* test.h

Since test.c does not exist, make prefers the built-in rule:

%.o: %.cpp
        $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $<

But would prefer this if it found it in the makefile:

%.o: %.cpp
	$(CC) $(CFLAGS) -c $<

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