Mail Archives: djgpp/2000/03/11/15:21:45
From: | Damian Yerrick <DONT DOT YOU DOT DAREd_yerrick AT hotmail DOT comSEND DOT SPAM>
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Newsgroups: | comp.os.msdos.djgpp
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Subject: | Re: AMD processors and assembly language
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Organization: | Pin Eight Software http://pineight.8m.com/
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Message-ID: | <qb2lcsc0ari409khrt7sdnehdl8i4uk05j@4ax.com>
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References: | <01JMWIIY2ZT69ASSJ4 AT SLU DOT EDU>
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NNTP-Posting-Date: | Sat, 11 Mar 2000 18:04:44 GMT
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Distribution: | world
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Date: | Sat, 11 Mar 2000 18:04:44 GMT
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To: | djgpp AT delorie DOT com
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DJ-Gateway: | from newsgroup comp.os.msdos.djgpp
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Reply-To: | djgpp AT delorie DOT com
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On Sat, 11 Mar 2000 10:22:23 -0600 (CST), GAMMELJL AT SLU DOT EDU wrote:
> In high precision arithmetic, the assembly language commands
>mul, div, and adc are essential. In the 486 architecture, these
>commands are efficient. In the alpha architecture, they do not exist.
WTF? Compaq's Alpha doesn't have multiply, divide, and add?
> AMD's 64-bit processors will follow the 486 architecture. Intel's
>will follow the alpha architecture.
No. The IA64 Merced Itanium chip is not a clone of the Alpha chip.
>As far as I am concerned, the AMD processor (code name sledgehammer)
>will be the processor of the future. The Intel processor (code name
>Itanium ?) is, unfortunately, not the processor of the future.
IA64 is a VLIW (very long instruction word) instruction set that uses
three execution units.
Each instruction is 128 bits long:
5 bits: control
41 bits: instruction to be sent to processor A
41 bits: instruction to be sent to processor B
41 bits: instruction to be sent to processor C
>I am willing to donate genprec to djgpp (or delorie.com) if anyone
>is interested.
That'd be great! Put it up on Simtel and tell DJ about it.
--
Damian Yerrick http://yerricde.tripod.com/
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