Mail Archives: djgpp/1998/11/13/16:30:23
I've got a rather obscure problem with some DPMI code, which hopefully
someone might have an answer to. Keir Fraser has been doing some work on
the FreeBE/AF video driver for Cirrus cards, and discovered a problem
with the use of memory-mapped IO registers that are located in the low
megabyte of physical memory (0xB8000). At the moment the CPU is caching
any writes to these registers, which obviously causes the hardware to
miss a lot of commands!
The DPMI spec says that a call to __dpmi_physical_address_mapping() must
disable caching for those pages, and this works fine for MMIO registers
in upper memory. But I can't map these IO registers, because they have
already been mapped as part of the conventional memory, and trying to
duplicate this mapping gives an error (actually I can double-map them
under win95, and this fixes the problem, but it is a very ugly
solution).
Is there any way to disable caching for a range of conventional memory
addresses? I can't find any mention of this in the DPMI spec, but would
hate to just give up on the idea and admit that this code will only work
under win95 DPMI :-)
--
Shawn Hargreaves - shawn AT talula DOT demon DOT co DOT uk - http://www.talula.demon.co.uk/
"Miracles are nothing if you've got the wrong intentions" - Mike Keneally
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