Mail Archives: djgpp/1998/08/26/13:32:26
On Wed, 26 Aug 1998 15:45:50 +0200 Vik Heyndrickx
<Vik DOT Heyndrickx AT rug DOT ac DOT be> writes:
>vcarlos35 AT juno DOT com wrote:
>> IIRC, Intel CPUs have special functionality for xoring a register with
itself.
>> It's something about avoiding a partial register stall after modifying
the
>> 32-bit extended register and than accessing the low-half of it using
>> the complementary 16-bit register. Could someone correct me?
>
>Never heard about, so it must be a post-Pentium feature. It could be
>true what you say, but it possibly couldn't influence the results of
>those instructions unless Intel would have really screwed up this one.
What I meant to say was that using xor would be preferable because not
only is the opcode smaller, but the resulting instruction would giver
more
flexibility in scheduling subsequent instructions on Pentium Pro/P2
processors.
>From "Intel Architecture Optimization Manual", Order Number 242816-003:
3.3 PARTIAL REGISTER STALLS ON PENTIUM ® PRO AND PENTIUM II PROCESSORS:
"On Pentium Pro and Pentium II processors, when a 32-bit register (for
example, EAX) is read
immediately after a 16- or 8-bit register (for example, AL, AH, AX) is
written, the read is
stalled until the write retires (a minimum of seven clock cycles)..."
"Special cases of reading and writing small and large register pairs are
implemented in
Pentium Pro and Pentium II processors ... The special cases are
implemented for XOR
and SUB..."
"xor eax, eax
movb al, mem8
add eax, mem32 no partial stall
xor eax, eax
movw ax, mem16
add eax, mem32 no partial stall
sub ax, ax
movb al, mem8
add ax, mem16 no partial stall
sub eax, eax
movb al, mem8
or ax, mem16 no partial stall
xor ah, ah
movb al, mem8
sub ax, mem16 no partial stall"
Karl
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