Message-ID:	<359ABF56.A4A4F046@rogers.wave.ca>
From:	Shaun Jackman <sjackman AT rogers DOT wave DOT ca>
Organization:	ARC Technologies
MIME-Version:	1.0
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: 64k demo
References:	<017d01bda453$6c3511a0$364e08c3 AT arthur>
Lines:	40
Date:	Wed, 01 Jul 1998 22:58:34 GMT
NNTP-Posting-Host:	cr549111-a.surrey1.bc.wave.home.com
NNTP-Posting-Date:	Wed, 01 Jul 1998 15:58:34 PDT
To:	djgpp AT delorie DOT com
DJ-Gateway:	from newsgroup comp.os.msdos.djgpp

> >What "arithmetic shift" really does depends on the signed integer
> >model of the processor. In a sign/magnitude implementation a 8 bit
> >signed int with the value -2 is
> >
> > 10000010
> >
> >A correct arithmetic shift left on this system would produce -4 alias
> >
> > 10000100
> >
> >too, because here it would mean "shift bits #0 to #6 only".
> 
> Correct.
> 
> >If signed integers are implemented as 2's complement as on INTEL based machines,
> >a "logical left shift" and an "arithmetic left shift" are the same
> >operation.
> 
> Wrong: logical shifting -2 (10000010) would give:
> 
> shift left -> 00000100  =  4
Sorry, you're wrong. The Intel 80x86 machines are 2's complement.
This means that -2 is 11111110. Shifted left this produces 11111100, or
-4.
SHL and SAL are the same bytecode on Intel 80x86.
CF <- register <- 0   (high bit is shifted into the CF (carry flag),
zero is shifted into the least significant bit)

SHR and SAR are different bytecodes however.
SHR produces
0 -> register -> CF    (0 is shifted into high bit, low bit is shifted
into CF (carry flag))
whereas SAR produces
sign bit -> register -> CF   (the sign bit is replicated in the high
bit, low bit is shifted into CF (carry flag))

> See? The sign bit "falls off" the end. Actually, it's stored in a carry or
> overflow bit.
> 
> shift right -> 01000001  =  65
> 
> These are obviously different to arethmetic shifts.
Only on the Motorola (and similar) chips. Not on the Intel 80x86.

I hope this cleared a few things up.
Shaun Jackman

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