Date:	Sun, 23 Nov 1997 15:29:01 +0200 (IST)
From:	Eli Zaretskii <eliz AT is DOT elta DOT co DOT il>
To:	Lemoine <mooncats AT firstdial-dontspamonme DOT com>
cc:	djgpp AT delorie DOT com
Subject:	Re: Suggestion for new feature in `make'
In-Reply-To:	<01bcf777$1d3ae860$902037cf@mooncats>
Message-ID:	<Pine.SUN.3.91.971123152844.19570Y-100000@is>
MIME-Version:	1.0

On 22 Nov 1997, Lemoine wrote:

> I am new to using make, so perhaps I am overlooking an existing feature,
> but I was recently remaking a program that was up-to-date with respect to
> its dependencies but which I had changed the makefile for.  When I ran make
> (no command-line arguments, version 3.76.1 for DJGPP), I received a message
> saying that my program was already up-to-date, even though I had not remade
> it since I had changed the makefile.

Make cannot know whether your change of the Makefile requires
recompilation, and if so, what should be recompiled.  Imagine a large
project with dozens of large source files: would you really want that
changing a comment in the Makefile will trigger massive recompilation
of everything?

If you know that every change in the makefile will require to
recompile everything, just mention Makefile as a dependency of every
target.

Another way would be to use the ``what-if'' feature.  For example, the
following command will force Make to rebuild every target which
depends on a file foo.h:

	make -W foo.h

Since you know which targets should be rebuilt after your change in
Makefile, you need to choose foo.h so that it will rebuild those
targets.  You can also have multiple -W options (-W foo.h -W bar.h
etc.).

> I checked through the documentation, and found no way of getting make to
> remake everything if the makefile is changed

Usually, to remake everything, you do this:

	 make clean
	 make

(Assuming that ``make clean'' removes all the products that are built
by default.)

> (which would be the general case for a changed makefile)

I don't agree with this being the general case.  See above.

> short of explicitly specifying it as a
> dependency in every rule.  This would be feasible fairly small makefiles
> such as mine, but very difficult for large ones.

Shouldn't be hard at all.  Examples (untested):

%.o: Makefile

SRCS = foo.c bar.c ...
OBJS = $(SRCS:.c=.o)
$(OBJS): Makefile

>  It would also break down if the makefile were renamed.

Any rule will break if a dependency is renamed.  Makefile is no
different.

> So, to those responsible for developing make:  how about a command-line
> option that specifies that make should consider the makefile as an implicit
> dependency in all rules?  Or, failing that, how about $(MAKEFILE) variable
> to at least be able to refer reliably to the makefile?

This request should be posted to <bug-gnu-utils AT prep DOT ai DOT mit DOT edu>, as
"make --version" says.  The Make maintainer(s) do not read this news
group.

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