From:	j DOT aldrich6 AT genie DOT com
Message-Id:	<199607312325.AA138645508@relay1.geis.com>
Date:	Wed, 31 Jul 96 22:54:00 UTC 0000
To:	ion2 AT freenet DOT hut DOT fi
Cc:	djgpp AT delorie DOT com
Mime-Version:	1.0
Subject:	Re: Makefile help..

Reply to message 0637303    from ION2 AT FREENET. on 07/31/96  7:19AM


>I'd like little to know about makefiles.. um.. could someone show
>an makefile-version of my compile bat file?
>
>gcc -Wall -m486 -O3 vesa.c -o vesa.o
>gcc -Wall -m486 -O3 gfx.c -o gfx.o
>gcc -Wall -m486 -O3 test.c -o test.o
>gcc -s vesa.o gfx.o test.o -o test.exe

Here's one that takes advantage of just about all of GNU make's
basic capabilities.   (Warning - make sure to use TABS, not spaces,
in your actual makefiles - I'm trying to save space here :)

Also, you may want to look at the makefiles that come with the
djgpp library source distribution, as well as the ones for many
other programs.  I haven't used any of make's built-in functions
in the below example, for instance.

John

---
# Start by defining your variables - the below are the traditional names.

# Programs generally go first:
CC = gcc

# Then flags:
C_FLAGS = -c -Wall -m486 -O3
L_FLAGS = -s
LIBS =

# Then files
O_FILES = vesa.o gfx.o test.o
S_FILES =
ALL_FILES := $(O_FILES) $(S_FILES)

# You should list any special target dependencies (like header files)
# here.  Know that if you don't specify commands for a rule, it can't be
# selected as the default, so make will continue until it sees the
# 'test.exe' rule.
# I'll give an example based on what you wrote above:
vesa.o : vesa.h
gfx.o : gfx.h
test.o : test.h
$(O_FILES) : main.h         # All object files will depend on this header.

# Now specify the primary target and its dependencies:
# In the below example, $@ is a special variable that resolves to the name of
# the current target file, i.e. 'test.exe'.
test.exe : $(ALL_FILES)
    $(CC) $(L_FLAGS) -o $@ $(ALL_FILES) $(LIBS)

# A little redundancy, or in case you want the unstubbed image for debugging:
# You may even want to exchange this rule with the previous one, depending
# on what your needs are.
test : $(ALL_FILES)
    $(CC) $(L_FLAGS) -o $@ $(ALL_FILES) $(LIBS)

# Now specify rules for individual targets.  Since you compile
# all your source files with the same command line, you can use a
# pattern rule to save typing.  The below example says that for
# each target with a .o extension, its primary dependency is the
# corresponding file with a .c extension.  The $< automatic variable
# corresponds to the name of the _first_ dependency of the current
# target.
%.o : %.c
    $(CC) $(C_FLAGS) $<

# Here's where you'd put any extra commands to install, clean up,
# or package your program.  A couple of examples follow:
clean :
    rm -f test *.o

extraclean : clean
    rm -f test.exe

# If you don't have 'rm' from GNU fileutils or another package,
# you'll have to use plain ol' DOS del in the above commands.

# Below, the '@' tells make not to echo the command.
install : test.exe
    update test.exe c:/programs/bin
    @echo Test is installed!

dist : test.exe
    pkzip ex test10b.zip readme test.exe c:/djgpp/bin/cwsdpmi.exe

all : test.exe install dist

# This is a special target which you should look up - essentially
# it tells make that the indicated targets aren't actually files and
# not to stop if it should somehow find a file by that name.
.PHONY : all clean dist extraclean install

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