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Mail Archives: djgpp/1993/08/14/07:28:08

Date: Sat, 14 Aug 1993 12:34:49 +0200
From: "Grzegorz B. Mazur" <gbm AT ii DOT pw DOT edu DOT pl>
To: djgpp AT sun DOT soe DOT clarkson DOT edu, eyal AT fir DOT canberra DOT edu DOT au
Subject: Re: SVGA page fault risk.

You should blame Intel for this, not DJ nor anyone else. The problem is that 
Intel x86 architecture RESTARTS instructions and page fault handling
wasn'designed especially for hidding VGA banking. The only solution is to
use byte accesses or aligned accesses. Note that using misaligned word transfers
should not be faster than using byte transfers, especially on CPUs with internal
cache.

Gregory

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