Mail Archives: djgpp-workers/2000/05/16/18:17:48
> From: "Dieter Buerssner" <buers AT gmx DOT de>
> Date: Tue, 16 May 2000 15:26:20 +0200
>
> > > When you "silently" return a NaN, say by log(-1.0), the bit will not
> > > be set in the status word.
> >
> > Are you sure?
>
> I tested it on my AMD K6-2. I will append some source.
>
> > The Intel manual seems to say otherwise: it says that
> > any invalid operation sets the appropriate bit in the status word.
>
> Loading a NaN into a FPU register seems not to be an invalid
> operation (which makes sense to me).
Intel's text is limited to a QNaN, the one which is produced as
invalid operations' masked response. If you tried that with an SNaN,
perhaps the behavior is different. But the FPU itself never produces
an SNaN.
> I find it rediculous, that a portable program must be
> aware of pow(NaN, 0) == 1.0.
Me too. I think this is one of the cases where we don't comply with
these requirements.
> > I believe that you interpret the word ``exception'' too literally
> > here. The C99 standard does not specify what does ``exception''
> > mean.
>
> This perhaps is a quality of implementation issue. In Annex H
> (informative) I read:
>
> C does require that SIGFPE be the signal corresponding to arithmetic
> exceptions, if there is any signal raised for them.
Sure, but note two things: (1) Annex H is _informative_, not
normative, and (2) it says "if there is any signal raised".
> Again, I don't think, that exceptions should be the default. Just
> give people, who wants them, the choice.
If it can be done without compromising the default, I don't object.
> With the following program I get the output:
>
> after silent inf x = Inf, sw = 0x00
> after trapping inf x = Inf, sw = 0x04
> after silent NaN x = NaN, sw = 0x00
> after trapping NaN x = NaN, sw = 0x01
I get the same, but we were talking about a NaN that resulted from an
invalid operation, like sqrt(-1). Loading a NaN forcibly is hardly an
interesting case, right?
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