Mail Archives: djgpp-workers/2011/06/23/03:53:42
On Wed, Jun 22, 2011 at 9:56 PM, Juan Manuel Guerrero
<juan DOT guerrero AT gmx DOT de> wrote:
> Am Donnerstag, 23. Juni 2011 schrieb Rugxulo:
>
>> "sil" is a AMD64 (64-bit long mode) register (isn't it?), so your GAS
>> must be confused with normal "si" and AT&T syntax "l" size postfix.
>
> si is the source index register.
> AFAIK sil = 8bit, si = 16bit, esi = 32bit, rsi = 64bit.
> The AT&T syntax "l" size postfix is applied to the opcode and
> not to the registers AFAIK. Â E.g. movl = 32bit move opcode.
>
> It should be noted that the bug appears if compiled with -O0.
> It compiles flawessly for -O1 and -O2. Â The same bug appears
> with GCC 4.6.0
>
> Regards,
> Juan M. Guerrero
>
The constraints for read_allowed and write_allowed should probably be
"=qm", not "=g", since the asm uses movb with these as parameters.
The compiler is allowed to pick any general-purpose register (or
memory) for the 'g' constraint, even ones that do not have byte parts
(like %si); 'q' is limited to register that have byte parts (%ax, %bx,
%cx, %dx).
-- Daniel Verkamp
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