X-Authentication-Warning:	kendall.sfbr.org: jeffw set sender to jeffw AT darwin DOT sfbr DOT org using -f
Date:	Wed, 23 May 2001 10:31:09 -0500
From:	JT Williams <jeffw AT darwin DOT sfbr DOT org>
To:	Bill Currie <bill AT taniwha DOT org>
Cc:	djgpp-workers AT delorie DOT com
Subject:	djasm and Intel's double precision shifts
Message-ID:	<20010523103109.D26660@kendall.sfbr.org>
Mail-Followup-To:	Bill Currie <bill AT taniwha DOT org>, djgpp-workers AT delorie DOT com
Mime-Version:	1.0
User-Agent:	Mutt/1.2.5i
Reply-To:	djgpp-workers AT delorie DOT com

Hi Bill,

In your version of `djasm', you refer to the double-precision shift
instructions as if they were shifts of an operand that is twice as
wide, e.g.:

        /* 16 bit shift double (ie 32 bit shift). */
        /* 32 bit shift double (ie 64 bit shift), can be either
           `shldd'/`shrdd' or `shldq'/'shrdq' */

But I'm hesitant to refer to Intel's `double precision' shifts as `double'
(32-bit) or `quad' (64-bit) shifts.  For example, the Intel documentation
says that the double-precision shift instruction

	SHLD	D2, D1, count

has the following effect:

- Shift D2 left by `count' bits.
- Fill the vacated LSB of D2 using the MSB of D1.
- Contents of D1 are not modified.

Because D1 is unchanged, this operation IMHO is not a true shift of a
monolithic 32- or 64-bit operand.  It's this feature that makes this a
double *precision* shift rather than just a `double' shift.

So IMHO the mnemonics for (and description of) these double-precision
instructions should be reevaluated.

TIA for any comments or suggestions.

jeff

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