Message-ID:	<19990812042350.B30327@tabor.ta.jcu.cz>
Date:	Thu, 12 Aug 1999 04:23:50 +0200
From:	Jan Hubicka <hubicka AT tabor DOT ta DOT jcu DOT cz>
To:	Eli Zaretskii <eliz AT is DOT elta DOT co DOT il>, Jan Hubicka <hubicka AT ta DOT jcu DOT cz>
Cc:	djgpp-workers AT delorie DOT com
Subject:	Re: Stack alignment
References:	<19990725134331 DOT A9005 AT tabor DOT ta DOT jcu DOT cz> <Pine DOT SUN DOT 3 DOT 91 DOT 990726092758 DOT 27650A-100000 AT is>
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In-Reply-To:	<Pine.SUN.3.91.990726092758.27650A-100000@is>; from Eli Zaretskii on Mon, Jul 26, 1999 at 09:28:19AM +0300
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On Mon, Jul 26, 1999 at 09:28:19AM +0300, Eli Zaretskii wrote:
> 
> On Sun, 25 Jul 1999, Jan Hubicka wrote:
> 
> > Also about binutils alignment.. I believe alignment is set to prety
> > low number there..
> 
> The subsection alignment is 4 bytes in current port of Binutils.
> 
> > next (after 2.95) version will need 32 byte alignment for AMD-K6 code
> > (to fit well into cache lines)
> 
> I believe we are heading for 16-byte alignment for the next version of
> Binutils.  This should be enough for all processors, including AMD-K6,
> since the prefetch queues fetch on 16-byte boundaries.  Is there
> something in AMD-K6 that makes this not good enough?
The target lignment according to doc is two instructions away from cache
line (32 bytes)..
> 
> Anyway, as long as GCC doesn't align the code on 32-byte boundary by
> default, there's not much sense in aligning subsections on 32-byte
> boundary, is there?
The gcc 2.96.1 in new_ia32_branch does alignment for k6 to 32 bytes by
default..

Honza

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