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From:	RayeR <glaux AT centrum DOT cz>
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: jitter between 2 hardware interrupt
Date:	Mon, 8 Mar 2010 17:04:26 -0800 (PST)
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> yes, but I test on 2 or 3 minutes and I have the jitter. I don't think
> that CPU clock change during this testing. But for a long test, I
> should be careful!

The TSC clock change problem may occur in some caces, e.g.:
- you start your program and perform TSC calibration but CPU was in
low power mode before. Then you make high CPU load and it will switch
clock to higher speed during your TSC calibration.
- everytime during the run may occur some condition that changes power
state, e.g. low battery or presence of AC power.
My NTB Compaq EVO 600 with PIII Tualatin mobile runs at 1,2GHz maximum
from AC power and 800MHz from battery. When I connect/disconnect AC
adapter the CPU clock changes.
- there may be some issues on multiprocessor/multicore systems where
every core has its separate TSC. I had managed to desynchronize TSC on
2 cores of my desktop E8400.

So IMHO TSC IS NO LONGER reliable source for timing...

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